Complementary current field-effect transistor devices and amplifiers

ABSTRACT

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a 35 U.S.C. § 371 National Stage Entry of,and claims priority to, International Application No. PCT/US2015/042696,filed Jul. 29, 2015, entitled “COMPLEMENTARY CURRENT FIELD-EFFECTTRANSISTOR DEVICES AND AMPLIFIERS,” the entire disclosure of which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a novel and inventive compound devicestructure, enabling a charge-based approach that takes advantage ofsub-threshold operation, for designing analog CMOS circuits.

Description of Related Art

The new millennium brings with it a demand for connectivity that isexpanding at an extremely rapid pace. By the end of year 2015, thenumber of global network connections will exceed two times the worldpopulation and it is estimated that in 2020 more than 30 billion deviceswill be wirelessly connected to the cloud forming the Internet of Things(or “IoT”). Enabling this new era are the revolutionary developments inmobile computing and wireless communication that have arisen over thelast two decades. Following Moore's Law, development ofhighly-integrated and cost-effective silicon complementary metal oxidesemiconductor (CMOS) devices allowed incorporation of digital and analogsystem elements, such as bulky Analog-to-Digital converters ortransceivers, into a more cost effective single chip solution.

In the last few years, however, while digital circuits have largelyfollowed the predicted path and benefited from the scaling of CMOStechnology into ultra-deep submicron (sub-μm), analog circuits have notbeen enabled to follow the same trend, and may never be enabled withouta paradigm shift in analog design. Analog and radio frequency (or “RF”)designers still struggle to discover how to make high-performanceintegrated circuits (or “ICs”) for ultra-deep sub-μm feature sizeswithout losing the benefits of shrinking size; including reduced power,compact footprint, and higher operational frequencies. Truly a paradigmshift is needed to break through the established science of analogdesign to meet the system on chip (SoC) demands of the new millennium.

Prior Art

The core building block of analog circuits is the amplifier. Discretecomponent amplifiers are free to use resistors, capacitors, inductors,transformers, and non-linear elements as well as various types oftransistors. Unwanted parasitics between various components are normallynegligible. However, in order to build amplifiers within an integratedcircuit, the normal analog circuit components are not readily available,and often take special IC process extensions to obtain these circuitelements if at all. The parasitics on integrated circuit amplifiers aresevere due to their close proximity and being coupled together throughthe silicon wafer they are integrated into. Moore's law IC processadvancements are focused on digital, microprocessor, and memory processdevelopment. It takes a generation (˜18 months) or two to extend the ICprocess to incorporate analog components, thus analog functionality isgenerally not included on the latest process single chip systems. These“mixed-mode” IC processes are less available, vender dependent, and moreexpensive as well as being highly subject to parametric variation. Ittakes substantial engineering to include sparse analog functionality onany IC which becomes specific to its IC vender and process node. Becauseanalog circuitry is carefully and specifically designed or arranged foreach process node, such analog circuitry is highly non-portable.Eliminating this limitation, analog circuit design engineers arebecoming scarce and are slowly retiring without adequate replacements.

Operational Amplifiers (or OpAmps) are the fundamental IC analog gainblock necessary to process analog information. OpAmps make use of a veryhighly matched pair of transistors to form a differential pair oftransistors at the voltage inputs. Matching is a parameter that isreadily available on an integrated circuit, but to approach the requiredlevel of matching, many considerations are used: like centroid layout,multiple large devices, well isolation, and physical layout techniquesamong many other considerations. Large area matched sets of transistorsare also used for current mirrors and load devices. OpAmps requirecurrent sources for biasing. OpAmps further require resistor andcapacitor (or RC) compensation poles to prevent oscillation. Resistorsare essential for the “R” and the value of the RC time constant isrelatively precise. Too big value for a resistor would make theamplifier too slow and too small results in oscillation. Constant “bias”currents add to the power consumed. In general, these bias currents wantto be larger than the peak currents required during full signaloperation.

As IC processes are shrunk, the threshold voltages remain somewhatconstant. This is because the metal-oxide-semiconductor (or MOS)threshold cutoff curve does not change with shrinking of the ICprocesses and the total chip OFF leakage current must be kept smallenough to not impact the full-chip power supply leakage. The thresholdand saturation voltage tends to take up the entire power supply voltage,not leaving enough room for analog voltage swings. To accommodate thislack of signal swing voltage, OpAmps were given multiple sets of currentmirrors, further complicating their design, while consuming more powerand using additional physical layout area. This patent introducesamplifier designs that operate even better as power supply voltages areshrunk far below 1 volt.

Prior art CMOS integrated circuit amplifiers are based on several analogor mixed-mode IC process extensions which are not available onall-digital IC processes. Primarily matched pairs of transistors areused as a differential inputs and current mirrors. These analog FETtransistors must be long, as depicted in FIG. 1q , to provide thenecessary high output resistance, and also must be wide in order tosupport the necessary current that is mirrored between them. Forexample, conduction channel 13 q which is operable by the gate terminal17 q must have a sufficient length or distance between the sourceterminal 14 q and the drain terminal 19 q on the body/substrate 16 q.Bias currents, which are normally larger than the peak analog signalcurrents, must be generated and maintained. Resistors and large areacapacitors are normally required to create references and stabilize theamplifiers. Because of parametric sensitivity, these designs are notvery portable between IC processes or venders. They are redesigned foreach IC process node and are very specifically tailored to their variousapplications. Due to their bulkiness amplifiers are normally thelimiting speed element of an IC system. What is needed is a scalabledesign that uses logic-only IC processes components, is processparameter tolerant, consumes a small area, uses relatively low power,and operates at voltages significantly below 1 volt. This is the subjectof the present invention.

The conventional MOS amplifier gain formation is an input voltagedriving a trans-conductance (g_(m)) which converts the input voltageinto an output current. This output current then drives an output loadwhich is normally the output of a current source for the purpose ofestablishing a high load resistance. This high resistance load convertsthe output current back into an output voltage. The resulting amplifiervoltage gain is g_(m)*R_(load). The equivalent output load resistance isactually the parallel combination of the load current source transistorand the amplifier output transistors. In order to keep this equivalentload resistance high, and the voltage gain high, these paralleltransistors must be very long, but to drive enough current, thesetransistors must be very wide to carry sufficient current also, thusvery large transistors are necessary. It also might be noted that theload resistance the amplifier output drives is also an additionalparallel resistance that reduces the voltage gain. It should also benoted that a load capacitance interacts with the amplifiers outputresistance, modifying the AC performance characteristics. What isactually needed is exactly the opposite of the present analog amplifieroperating principles of very small voltage-input to high-impedancecurrent-output (g_(m)); which the present invention is about: very smallcurrent-input to low-impedance voltage-output (r_(m)). FIG. 1a is atransistor level schematic diagram of a high-quality MOS IC OpAmp as abaseline reference (Gray, Paul R. et al., “Analysis and Design of AnalogIntegrated Circuits,” 5^(th) edition, John Wiley & Son Ltd, at pg. 484)which is used for comparison in the description of the amplifiersillustrated herein.

The baseline comparisons are (all made in a 180 nm IC process) in theform of performance plots as in: a Bode Gain-Phase plot FIG. 1b , whenV_(dd)=1.8 Volts and R_(cmp)=700 ohms. Wherever possible all the axisscales for each of these three comparison plots are kept the same. A 180nm process was selected for comparison of all the comparative examplesin this specification because conventional prior art amplifiers workbest and have had the most usage to mature the analog mixed-mode ICprocess extensions offered as required for conventional analog. Also asthe IC process is shrunk and the power supply voltage is decreased, thisis where the implementations of the present invention become highlybeneficial.

Normally MOS amplifiers operate within a square-law form due to thestrong-inversion MOS transistor square-law characteristics; these arenot very well defined or predictably stable to the degree that analogcircuits need. Exponential-law operation, like bipolar transistorsoperation is higher gain, stable, and well defined. At very weakoperating conditions, MOS transistors convert to exponential operation,but they are too slow to be of very much use. Furthermore, the“moderate-inversion” transition between these two operating mode providenon-linarites that lower the quality of analog MOS circuits. At thethreshold voltage, where MOS transistors operate around, is where 50% ofthe current is square-law and the other 50% is exponential. This is thedefinition of threshold voltage in the latest MOS simulation equations.Full exponential MOS operation at high speed would provide higher gainthat is predictable, stable, and well defined. This patent is about fastamplifiers that operate in the exponential mode but not inweak-inversion; instead a super-saturated mode is introduced.

To understand the prior art, let's begin with a discussion of weak vs.strong-inversion (Enz, Christian C. et al., “Charge-based MOS TransistorModeling—The EKV model for low-power and RF IC Design, John Wiley & SonLtd., 2006). Referring to FIGS. 1e and 1f , weak-inversion is the rangewhere most designers would consider the transistor to be OFF:

-   -   Weak conduction channel inversion 13 e occurs when the Gate 17 e        on the body/substrate 16 e is operated below its threshold        voltage V_(threshold) 17 f in FIG. 1f with channel ionization 13        e characterized by a thin surface layer;    -   Source 14 e to Drain 19 e voltage 19 f is small (typically less        than 100 mV);    -   For weak-inversion, the gate G 17 e is typically operated by        gate voltage supply 12 e at a low potential (˜300 mV);    -   This creates a channel surface conduction layer 13 e, of uniform        depth from source S 14 e to drain D 19 e;    -   Since there is essentially zero voltage gradient along the        channel 13 e (˜no electric field), any current between drain D        19 e and source S 14 e is primarily supported by diffusion;    -   Increased gate voltag Vgs 12 e at the gate G 17 e increases the        thickness of the conduction layer 13 e below the gate 17 e, thus        allowing more charge to diffuse along the channel 13 e;    -   The conductivity of this surface layer is exponentially related        to the gate voltage Vgs 12 e at the gate G 17 e;    -   This exponential relationship holds over as many as 6 decades of        dynamic analog signal range for the drain channel current;    -   The channel appears as a moderately high value resistor for its        channel current (many 100⁺s of K-Ohms);    -   The resulting uniform conduction channel depth promotes higher        exponential gain but at a severe speed penalty due to low        current density; and    -   This weak-inversion conduction is reflected in a near zero        operating point 13 f in FIG. 1 f.

Strong conduction channel inversion occurs when the gate voltage Vgs 12g at the Gate 17 g on the body/substrate 16 g is operated above itsthreshold voltage 17 h (referring to FIGS. 1g and 1h ) with channelionization characterized by a graduated conduction channel, deeper nearthe Source 14 g and shallow near at the Drain 19 g:

-   -   Strong conduction channel inversion 15 g and 15 h occurs when        the Drain 19 g to Source 14 g voltage 19 h is larger than the        threshold V_(threshold) 17 h in FIG. 1h (typically in excess of        400 mV);    -   The Gate 17 g is operated above its threshold voltage        V_(threshold) 17 h in FIG. 1 h;    -   In strong-inversion 18 g, the Drain 19 g voltage is typically        operated above the Gate 17 g voltage which results in a        pinched-off conduction channel 15 g near the Drain 19 g;    -   This pinched-off channel at 15 g gives rise to high output        impedance at the Drain 19 g and can be observed as the thick        flat part 18 h of the operating characteristic plot FIG. 1 h;    -   As the Drain 19 g voltage V_(d) is changed, the pinched-off        region 15 g changes length, but its thin conduction layer is        retained, keeping the output impedance high;    -   Due to the Gate 17 g to channel 15 g voltage and the electric        field along the conduction channel path (Drain 19 g to Source 14        g), the conduction channel 15 g is forced deeper at the Source        14 g and tapers to near pinch-off at the Drain 19 g;    -   The resulting conduction layer behaves with a Square-law        response to the gate voltage at the Gate 17 g;    -   In strong-inversion, dynamic range of channel current is limited        to about 2 or 3 decades; the channel must drop into        weak-inversion for additional dynamic range; p1 This        strong-inversion conduction channel 15 g appears as an        adjustable current source (high value resistor); and    -   The wedge shape of the conduction channel 15 g provides high        speed from high current density, but requires the carriers to        transit the channel and velocity saturation is reached limiting        the speed or cutoff frequency of the transistor; and    -   This is reflected as the operating point 15 h in FIG. 1h which        is along its bolded line 18 h.

FIG. 1e , shows the channel development under weak-inversion conditions.The conduction channel has a relatively even distribution of carriersover its entire length and width. Note that the conduction 13 e depth ofthe entire channel is the same as the pinch-off area 15 g on the rightchannel side (or near the drain 19 g) of FIG. 1g . The output drainvoltage Vd loaded on the drain D 19 e by bias current, I_(bias) Ld19 e.This thin conduction layer 13 e contributes a significant amount ofnoise because the channel current travels along the surface where defecttraps are concentrated. The Gate 17 e to channel voltage V_(g) in FIG.1e has a strong (exponential) effect on the density of carriers in thisconduction layer 13 e.

FIG. 1f shows a plot which has an exponential relationship of draincurrent I_(d) to drain voltage V_(ds) using a fixed gate voltage V_(g).It is to be noted that the drain voltage V_(ds) must be limited to asmall value (on the order of 100 mV) in order to stay in weak-inversion.

FIG. 1g shows channel 15 g ionization under strong-inversion conditions.In strong-inversion, there is an output drain voltage V_(d) loaded onthe Drain 19 g by an output load: I_(bias) Ld19 g. This load presents alower potential difference between Gate 17 g and Drain 19 g end of theconduction channel 15 g than the potential difference between the Gate17 g and Source 14 g end of the conduction channel, resulting in atapered conduction channel 15 g. The conduction channel thins down to aminimum as it approaches the drain provide a high output resistance.This output resistance is primarily defined by the thin channelcross-sectional area. As the drain voltage is varied, this thinpinched-off length of the channel changes, but not so much itscross-sectional area. This leads to a high output resistance, in thatDrain 19 g output resistance variation with drain voltage is relativelysmall, yielding a high output resistance. This high resistance isrequired in conventional g_(m) analog MOS circuit design. In thispinched-off channel region, the carriers approach their velocitysaturation, thus limiting their transit time along the channel. This iscalled “channel length modulation” (the flat part of the channel 15 g),resulting in pinch-off near the drain diffusion where the channelreaches a thin layer at 15 g. The pinch-off region, where the carriersare forced to the top of the channel, imparts significant noise by meansof surface defect carrier traps. The higher the drain voltage V_(d), thelonger the pinch-off region and thus the higher the contributed noise(Rahul, Sarpeshkar, “Ultra Low Power Bioelectronics-Fundamentals,Biomedical Applications, and Bio Inspired Systems”, ISBN9780521857277,and Lee, Thomas “The Design of CMOS Radio-Frequency IntegratedCircuits”, 2nd Ed, Cambridge ISBN-13 978-0521835398), thus is desired tokeep this voltage low for low noise contribution to the channel current.Other effects such as velocity saturation and hot electron jumping overto the gate oxide are noted around this thin saturated region, thus itwould be highly desirable to minimize this region by lower voltage andsemiconductor doping profiles.

FIG. 1h shows a characteristic plot which approaches a “constantcurrent” relationship between drain current I_(d) and drain voltageV_(ds) with a fixed Gate voltage V_(g) on the gate G. It is to be notedthat the drain voltage V_(ds) spans a much larger range of nearly thepower supply voltage V_(dd), while maintaining the same current.

A two-finger CMOS inverter is illustrated in FIGS. 1i, 1j, 1k, 1m, and1n . A logic inverter possesses several desirable properties:

-   -   They exist in all logic IC processes    -   are the most common and fundamental building block    -   highly scalable    -   process parameter drift tolerant    -   small    -   high speed    -   high output drive for varying capacitive loads    -   arguably the highest gain of a complementary pair of MOS        transistors    -   low power    -   easily used

A basic two finger inverter schematic of the prior art is depicted inFIG. 1i . For example, Vin 10 i of the basis two finger inverter 100 isconnected to the gate terminals of NFET 101 and PFET 102. The sourceterminal of NFET 101 is connected to negative power voltage, and thesource terminal of PFET 102 is connected to positive power voltage. Thedrains of NFET 101 and PFET 102 are connected together to form an output19 i. A generic physical layout is illustrated in FIG. 1k in parallelwith another inverter schematic diagram in FIG. 1j which has beenstretched out and aligned alongside the physical layout to correlate theinverter schematic FIG. 1j to the physical layout structure FIG. 1k .Artistic liberty was used to clearly relate these two figures. Actualphysical layout would be in accordance of the design rules and practicesof the IC process it is designed for. FIG. 1m is a 3-D sketch of thephysical layout. FIG. 1n shows a cross-section view of the physicallayout as indicated Section AA in FIG. 1m . The two finger inverter 100includes a common gate terminal 10 j/10 k/10 m/10 n, and output 19 j/19k/19 m/19 n connected to drain terminal D− 11 j/11 k/11 m/11 n and D+ 12j/12 k/12 m/12 n. As can be seen in FIGS. 1k to 1n , the drain D− 11k/11 m/11 n is displaced between the source terminals, S− s13 k/s13m/s13 n and s15 k/s15 m/s15 n, while the drain D+ 12 k/12 m/12 n isdisplaced between the source terminals, S+ s16 k/s16 m/s16 n and s14k/s14 m/s14 n. The pull down transistor channel 13 k/13 m/13 n is inparallel with 15 k/15 m/15 n, while the other pull down transistorchannel 14 k/14 m/14 n is in parallel with 16 k/16 m/16 n. The polytransistor control gate 17 k/17 m/17 n is in communication with the gateterminal 10 k/10 m/10 n. Drain diffusions 12 n are shown in FIG. 1n .The charge distribution in the drain channels 13 n, 15 n, 14 n, and 16 nare shown in FIG. 1n . This charge distribution is illustrated for thevoltage where the logic is in the middle or most active part of itsstate change. This charge distribution is an extension of the chargedistribution in FIG. 1g . These inverter figures are closely related tothe present invention as the basis for making minor alterations that donot require any IC process modification as will be developed below.

FIG. 1p illustrates a prior art MOS structure that turns out to actuallyemulate a combination of both modes of operation; strong-inversion FIGS.1g, 1h with enhanced weak-inversion-like properties of FIGS. 1e, 1f .This structure is inherent in a 2-finger inverter as shown twice in theFIG. 1k physical layout abstraction. For reasons that will be developed,this structure will be named an iFET (MOSFET with a current inputterminal=i) where the MOS structure is employed for the presentinvention.

Although similar MOS structures appear in prior art, no significantexploitation of many of its unique properties are known or published. Inaddition, proper biasing remains as a problem(s) for its operation(s). Adeeper understanding of the internal mechanisms resulted in discovery ofmany desirable applications (enabling superior operation atdeep-sub-micron scale), including an approach to proper biasing thattakes advantage of natural equilibrium. This natural equilibrium is theresult of a “PTAT”/“CTAT” (proportional to absolutetemperature/complement to absolute temperature) known as a “Band-Gap”voltage reference mechanism, again functional at deep-sub-micron scale.

Some references show a MOS field effect device includes a body/substrate16 p, the source terminal 14 p and drain terminal 19 p on the body 16 p.The gate terminal 17 p is placed between the source terminal 14 p andthe drain terminal 19 p for controlling conductivity therebetween. Thedevice further includes two identical regions 13 p and 15 p of like“conductivity type” separated by a diffusion region 11 p (designated asZ for Low Impedance in the prior art) as shown in FIG. 1p . Non-patentliterature, Pain, Bedabrata et al., “Low-power low-noise analog circuitsfor on-focal-plane signal processing of infrared sensors”, the JetPropulsion Laboratory, California Institute of Technology, and theDefense Advanced Research Projects Agency and the National Aeronauticsand Space Administration; and Baker, Jacob et al., “High Speed Op-ampDesign: Compensation and Topologies for Two and Three Stage Design”,Boise State University, for example, shows such a structure. However,these references do not exploit any opportunities as shown in thispresent invention, especially when complementary devices like this arecombined into a single composite device structure as will be explainedin this invention. Such configurations have been called self-cascadingor split-length devices. The two conduction regions of such aconfiguration are arranged between source and a drain diffusions andhave both a high impedance common gate connection and a low impedance Zconnection to the mid channel region. This low impedance mid channelcontrol input/output Z, when exploited as outlined in this document,enables an entirely new set of analog design methods and capabilities.

Although a cascode amplifier can be found in prior art, the prior artdoes not contain a complementary pair of cascode transistors connectedas a totem-pole. With this simple compound device structure, feedbackfrom the output to the input can be used to self-bias the resultinginverter into its linear mode. As mentioned above in association withFIG. 1a , the biasing of an amplifier by means of current mirrors hasalways been problematic; however, the novel and inventive self-biasingstructure of the present invention addresses such an issue. Advantagesof the configuration of the present invention (referred to as acomplementary iFET or CiFET) are many, including, but not limited to:

-   -   Gain of the single stage is maximum when the output is at the        midpoint (self-bias point);    -   The gain of a single CiFET stage is high (typically approaching        100), therefore, while the final output may swing close to the        rails, its input remains near the midpoint where the gain is        high.    -   When used in a series chain of CiFET devices, all earlier stages        operate with their inputs and outputs near the mid-point        (“sweet-spot”) where the gain is maximized;    -   Slew rate and symmetry are maximized where the channel current        is highest (near the mid-point);    -   Noise is minimized where the channel current is highest (near        the mid-point); and    -   Parasitic effects are negligible where the voltage swing is        small.

When the gate input signal moves in one direction, the output moves inthe inverse direction. For example; a positive input yields a negativeoutput, not so much because the N-channel device is turned on harder,but rather because the P-channel device is being turned off. AThevenin/Norton analysis perspective shows that the current through theP and N devices must be exactly the same, because there is nowhere elsefor drain current in one transistor to go except through the drain ofthe complementary transistor; however the voltage drop across thosedevices does not have to be equal, but must sum to the power supplyvoltage. Due to the super-saturated source channel, these voltages aretied together exponentially. This is even more evident at low powersupply voltages where the voltage gain peaks due to the conductionchannels being forced into a diffusion mode of operation similar toweak-inversion. This means that the gate-to-source voltage is preciselydefined by the same and only drain current going through bothtransistors. Exponentials have the unique transparent physical propertylike as with a time constant, or “half-life;” It does not matter where avalue is at a given point of time, a time constant later the value willbe a fixed percentage closer to the final value. This is a “minds-eye”illustration of the primary contributor to output movement in responseto input change. This same current balance of gate-to-source operatingvoltages also indicates why the “sweet-spot” in the self-biasedamplifier is so repeatable. In effect it is used as a differentialpair-like reference point to the amplifier input signal.

Briefly stated, the operation of the conventional CMOS amplifier of FIG.1a is as follows:

In operation, differential analog input voltages are applied toInput+10a and Input−11a of a precisely matched pair of transistors Q1 aand Q2 a respectively. Any mismatch in these two transistors appears asa DC voltage added to the differential input. If there is 1 millivolt ofmismatch, which is very hard to meet in CMOS, and the amplifier has again of 1000, the output voltage error will be 1 volt. In newer ICprocess nodes, power supplies are already limited to less than a volt.Exotic double centroid physical layout with multiple identicaltransistors arranged in diametrical opposition and everything elsepossible symmetrically possible are needed in the physical layout of thedifferential pair to minimize the offset voltage.

These amplifiers function by steering and mirroring bias currents from acurrent source 12 a between their transistors. All the bias currentshave to be larger than the peak signal deviations and these currentsalways flow. These currents also have to be large enough to drive theinternal capacitive load of the amplifier's internal transistors plusinterconnect, not to mention the output drive current which comprisesthe capacitive load at the maximum bandwidth frequency or slew rate.

The first bias current mirror input transistor is a transistor Q8 awhich is “diode connected” in that its gate and drain are tied togetherand bias at a threshold voltage below the top power supply rail. Thisbias voltage is applied to the gates of two transistors Q5 a, Q7 aadditional positive rail based current mirrors that have to be matchedto a lesser degree. In order to progressively increase the mirroredcurrents from the bias current mirror input transistor Q8 a to thedifferential current feed transistor Q5 a to the output pull-up currenttransistor Q7 a, the transistors Q5 a and Q7 a are actually multipleinstances connected in parallel. A double for the transistor Q5 a and aneight (8) times for the transistor Q7 a are typical choices for thesemultiples.

The differential pair of the transistors Q1 a, Q2 a is used to split thebias current to the transistor Q5 a equally at the zero differentialvoltage input where the amplifier strives for. To achieve a voltage gainin analog designs, a positive drive current is balanced against anegative drive current. The differential pair of transistors Q1 a, Q2 aachieves this by mirroring transistor Q3 a of the outputs back to theother leg of transistor Q4 a, making current opposition with thetransistor Q2 a. Voltage gain is g_(m)*R_(L) where R_(L) is the parallelcombination of the output impedance of the transistors Q4 a and Q2 a.For analog MOSFET transistors to present a high impedance on theiroutput, they need to be very long because the depilation width due todrain voltage modifies the conduction channel length near the drainterminal. This is called “channel length modulation” which is similar tothe bipolar “Early voltage” named by Jim Early of FairchildSemiconductor during the early bipolar days. For this high outputimpedance requirement, the transistor Q4 a must be long, and it alsomust be equally wide to preserve its gain setting the basic transistorsizing of the amplifier. This size must be set equal for the transistorsQ3 a and Q6 a, except the transistor Q6 a must also include the multipleused for the transistors Q5 a to Q7 a along with a factor of two to makeup for the split of current by the differential pair. In equilibrium,the gate voltage on the transistor Q6 a wants to be the same as the gatevoltage on the transistors Q3 a, Q4 a looking like a pseudo-currentmirror arrangement at the bottom power supply rail.

There are still many other linear amplifier circuit designconsiderations beyond these basic principles like stabilityconsiderations by compensation resistance or R_(comp) 15 a andcompensation capacitance or C_(comp) 16 a and power supply noiserejection. As can easily be envisioned, the design of analog circuits inan IC is quite involved, process parameter dependent, and not veryportable between IC processes.

The resulting linearity of these amplifiers are also limited due todifferent non-linear characteristics between the gain device and theload device (pull-up and pull-down) which cannot cancel each other out.The CiFET device structure, which is the present invention to beexplained later in this specification, loads itself with the same devicestructure, except that the combination obtains its complementary naturethrough the use of opposite semiconductor diffusion types whichinherently and precisely mimic any non-linear characteristics with theopposite sign to cancel each other's linearity deviations out. CMOSinverters get their opposing drive through the opposite semiconductordiffusion type, thus are a good foundation to base linearity on. This isbecause the same current is carried through one transistor is alsopassed through the complementary device. Inversion is obtained throughopposite diffusions.

It is to be noted that during the transition from vacuum tubes tobipolar transistors the industry underwent a major paradigm shift,learning to think in terms of current rather than voltage. With theadvent of FETs & MOSFETs the pendulum swing is back toward thinking interms of voltage, but much knowledge has been lost or forgotten. Hereinis contained the rediscovery of some old ideas as well as some new ones,all applied to the up-coming “current” state of the art. It is believedthat the inherent simplicity of the present invention speaks to theirapplicability and completeness.

A first issue may be that there is always a need for a little analogfunctionality, yet nearly all analog performance metrics of a MOStransistor are remarkably poor as compared to that of a Bipolartransistor. The industry has made MOS devices serve by employingextensive “work-arounds.” Conventional analog design is constrained byone or more of the followings:

-   -   Power supply voltages sufficient to bias the stacked thresholds,        and transistors large enough to supply the necessary low output        impedance, or high output impedance for gain and linearity.    -   Process extensions (unavailable at deep sub-μm scale) to        function at all, let alone with the enhanced performance,        demonstrated herein.    -   Resistors, inductors, and large capacitors are mostly        non-existent for analog designs in newer IC processes.

In contrast, bipolar transistors can be made to have high gain (β),wider bandwidth, wider dynamic range (many decades, from near the railsdown to the noise floor), better matching (required in differentialpairs), and band-gap references. Junction FETs, which operate withsub-surface channel conduction below the surface defects, have lowernoise than bipolar transistors. Likewise the iFET super-saturated sourcechannel operates primarily below the defects at the channel surfaceunderneath the gate oxide.

MOS designs are poorer in the above areas but have their own extremeadvantages, including, but not limited to:

-   -   MOS devices are small    -   highly scalable    -   high speed    -   low power    -   ultra-dense/high functionality systems on a chip, where Bipolar        designs cannot go (deep sub-μm scale).

Accordingly, building analog circuits on an IC has always beenproblematic. Engineering around poorly performing analog components hasbeen the overriding objective for analog IC designers since analogcircuits have been integrated. This drove the need for digital signalprocessing with algorithm development yielding digital magic.

Today the real-world of analog circuit design signals still needs to beconverted, on both the front and back end of signal processing systems.This need has become a road-block at deep sub-μm scale.

Another problem may be that solid-state amplifiers have been notoriouslynon-linear since their inception. To make them linear, increased openloop gain (with levels significantly higher than is ultimately needed)is traded for control over actual circuit gain and linearity through theuse of a closed loop (feedback). A closed loop amplifier requiresnegative feedback. Most amplifier stages are inverting, providing thenecessary negative feedback. A single stage, with a closed loop, isstable (does not oscillate). Increased loop gain requires that stages beadded such that there are always an odd number of stages (sign isnegative), to provide the necessary negative feedback. While a singlestage amplifier is inherently stable, three stages and most definitelyfive stages are unstable (they always oscillate).

The problem then is how to properly compensate a multi-stage closed loopamplifier while maintaining a reasonable gain-bandwidth product. This isparticularly difficult at deep-sub-micron scale where circuit stagesmust be simple in their design. The severely limited power supplyvoltages preclude the use of conventional analog design approaches.Additionally, it is desirable to avoid reliance upon analog extensionsbut rather to accomplish the necessary analog functions using alldigital parts, to improve yields and decrease costs. Using all digitalparts allows analog functions at process nodes that do not yet haveanalog extensions, and may never have them.

There is a long felt needs for low-cost/high-performance systems on asingle chip to realize, affordable high-volume devices such as theInternet of things, smart-sensors, and other ubiquitous devices.

SUMMARY OF THE INVENTION

The present invention relates to a novel and inventive compound devicestructure, enabling a charge-based approach that takes advantage ofexponential relationships of a super-saturated source channel describedin relation to FIGS. 2a, 2b and 2e to 2m below which possessessub-threshold like operation when used for analog CMOS circuit designs.The sub-threshold like operation offers current input to voltage outputtrans-impedance functionality with interesting properties.

Through incorporating this compound device structure 200 as shown inFIG. 2m into an inverter, the present invention is an evolution of anordinary CMOS inverter. It provides extremely high precision, speed,linearity, low voltage operation, low noise, and a compact physicallayout, using an all-digital IC process that naturally extends into deepsub-μm IC process nodes. In addition to the expected digital inverterfunction, several classes of analog circuits are facilitated: a voltageinput to voltage output amplifier, a current input to voltage outputamplifier, an analog adder, an analog multiplier, a spectrally-puresine-wave multi-phase oscillator controlled through an adjustable delaycircuit, and a Voltage or Current reference source which includestemperature measurement or temperature independence. It is envisionedthat the present invention may open up the possibility of integratedanalog signal processing at logic speed, thus enabling the continuationof microprocessor capability according to Moore's law. Take special notethat analog functionality is realized, in a digital IC process, using asingle optimized digital logic circuit cell.

A preferred embodiment of the present invention 300 provides for astacked pair of transistors with a common gate 301, mirrored with acomplementary pair of stacked transistors 302 FIGS. 3a, 3b, 3c, 3d, 3e(like a digital inverter 100 in FIGS. 1i, 1j, 1k, 1m, 1n ), withfeedback from its own output to establish an optimum bias point. Thisconfiguration offers additional trans-impedance control inputs thatrespond to current rather than voltage and so provides an idealconnection for symmetrical roll-off compensation in a multi-stageamplifier. This embodiment also provides extreme linearity as well as alow impedance voltage output that is essentially insensitive tocapacitive loading. Drawing inspiration from the past, conceptsdeveloped for the chopper stabilized amplifier are rediscovered and maybe applied to lend an element of gain, accuracy, and stability uncommonin the industry.

According to one aspect of the present invention, a CiFET amplifier isprovided, which is a basic Analog-in-DIGITAL building block. It isimpractical to try to construct analog systems at small scale using thesame system design techniques that have been previously applied atlarger scales. The power supply voltage is too low to provide a dynamicrange needed to swing analog voltages, and the required analog ICprocess extensions are not available. In the newest ultra-deep sub-μmprocesses, long and wide transistors are not available, often all theall the individual transistors must be identical in size. The solutionis to convert analog signals to digital as early as possible and takeadvantage of digital signal processing techniques that are availabletoday. To accomplish this it is necessary to have a reliable, precisionfront-end and that requires a high-precision amplifier. The techniquesin this specification point to such a solution.

According to another aspect of the present invention, it takes advantageof the Doping Profile and Ratioing. Not everything in optimizing acircuit has to do with the circuits' electrical configuration. Properdevice sizing and especially coarsely adjusting the size relationshipbetween complementary transistors provides considerable performancebenefits. As will be developed in this specification, the CiFET, being acompound device structure, offers extensive opportunity to establishimpedance matching and gain control through proper ratio of the physicaldevice parameters. Other important characteristics, like noise, speed,and power, can be tailored through careful specification of the physicalconstruction and doping of the transistors, rather than relying solelyon circuit configuration.

According to yet another aspect of the present invention, certain noiseadvantages are provided. In the end, it comes down to signal-to-noiseratio. Low power supply voltage requirements in ultra-deep-sub-μm ICprocesses limit the maximum signal swing to a much smaller number thanmost analog designers are used to. So with a smaller signal, thelow-noise techniques embodied herein must be employed in order tomaintain the desired signal to noise ratio or perhaps even improve theratio.

Simply stated, the CiFET device starts with a common 2-finger inverterand re-wires the inverter's parallel transistor connections to series,making these intermediate series transistor connections available tospawn a supplementary pair of input/output terminals. These newterminals (referred to as iPorts) are observed to be particularlysensitive to charge transfer (or current) and exhibit ultra-linearanalog trans-impedance (input current to output voltage) response, amongmany other interesting analog properties observed. In a manner similarto an inverter, the output can handle varying high capacitive loads withminor degradation—highly desirable for analog portability. The sizingand rationing of the individual transistor conductance can be roughlyoptimized to enhance various analog performance metrics.

Traditionally analog MOS circuits convert input voltage to outputcurrent (g_(m)), which is then turned back into a voltage by means of anopposing high impedance load; high impedance is needed in order toobtain voltage gain. This results in vastly different gain path versesload path which is made up of nonlinear structures. Thus, a mismatch inoutput pull-down and pull-up signals come from fundamentally differentcircuits in order to obtain the signal polarity inversion needed todrive the output up or down. This not only restricts the linearity ofthe amplification, but the dynamic output swing, and takes appreciablepower causing substantial design effort to create at best with poorportable and flawed performance among many other things.

On the other hand, as in a CMOS inverter, the CiFET derives its opposingload by means of opposite diffusion types, not different types ofcircuits. Both the pull-up and the pull-down circuits are not only theequivalent, but they pass the same current when equilibrium is reached,thus matched circuits passing the same current cancel out nonlinearitiesleading to minimum distortion over extreme ranges of operation. As inCMOS logic, opposing signals come from opposite diffusion types. Inaddition the CiFET operates with opposing exponential equalities thatenable interesting mathematical operations that are valid over anexciting wide range.

BRIEF DESCRIPTION OF FIGURES

FIG. 1a illustrates a high quality CMOS OpAmp prior art transistorschematic from a prominent textbook “Analysis and Design of AnalogIntegrated Circuits,” 5^(th) Ed, by Gray, Hurst Lewis and Meyer, p484 asa prior art amplifier for comparison;

FIGS. 1b to 1d are a baseline set of representative performance plotsillustrating frequency domain performance and power supply dependency ofthe prior art OpAmp of FIG. 1 a;

FIGS. 1e and 1g show cross-sectional views of prior art MOSFET channelconstruction weak-inversion and strong-inversion, respectively, andFIGS. 1f and 1h show plots showing exponential relationship betweendrain current and drain voltage when weak-inversion and whenstrong-inversion, respectively;

FIG. 1i shows schematic diagram of a prior art 2-finger invertor;

FIGS. 1j and 1k show physical layout abstractions of the 2-fingerinverters shown in FIG. 1 i;

FIG. 1m shows a three (3) dimensional perspective view of the 2-fingerinverter of FIG. 1 i;

FIG. 1n shows cross-sectional view at Section AA shown in FIG. 1 m;

FIG. 1p shows a physical layout of a prior art split channel MOStransistor;

FIG. 1q shows a three (3) dimensional perspective view of a prior artlinear MOS field-effect transistor;

FIG. 2a illustrates a three (3) dimensional prospective view of a MOSfield-effect transistor (or iFET) with a new mid-channel bi-directionalcurrent port (iPort) of the present invention;

FIG. 2b illustrates a cross-sectional view of iFET of the presentinvention with visualized channel charge distributions;

FIG. 2c shows a graph of drain voltage Vas and drain current Id whenthere is no iPort injection current, while FIG. 2d shows another graphwhen max iPort injection current is provided;

FIG. 2e illustrates how the new iPort current terminal replaces half ofa differential pair in an iFET amplifier of the present invention;

FIGS. 2f to 2L illustrate channel ionization and trans-impedancecharacterization of the iFET along with suggested schematic symbols;

FIG. 2m illustrates a schematic diagram of a trans-impedance iFETamplifier of the present invention;

FIG. 3a illustrates a schematic diagram of complimentary pair of iFETsof the present invention;

FIGS. 3b and 3c illustrate a physical layout abstraction of thecomplementary iFET (or CiFET) compound device shown in FIG. 3 a;

FIG. 3d shows a three (3) dimensional perspective view of the CiFETcompound device shown in FIG. 3 a;

FIG. 3e illustrates cross-sectional view at Section AA of FIG. 3 d;

FIGS. 3f and 3g illustrate a CiFET operational modeling and a suggestedschematic symbol therefor;

FIGS. 3h to 3k illustrate various CiFET compound device transfercharacteristics and properties of the present invention; and

FIG. 3L illustrates the availability of self-biased reference voltageterminals;

FIG. 3m illustrates the wide range and linearity of the PTAT temperaturemeasurement characteristics of the PTAT self-biased reference terminalof FIG. 3L;

FIG. 3n and FIGS. 3p to 3w are representative performance plots of theCiFET compound device illustrations of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A MOS structure referred to herein as an iFET, where the letter “i”refers to a current and “FET” refers to a Field Effect Transistor, isthe enabling element of several high performance and novel designs ofthe present invention. The present invention is based on the addition ofa direct connection to a mid-point in a Field Effect Transistor (or FET)channel and the realization that this is a low impedance port (currentport, or herein referred to as “iPort”) having trans-impedance currentinput to voltage output gain properties realized by providing abidirectional current sink/source mid-channel with a very low inputimpedance at a low saturation voltage, and additionally connectingreciprocal iFETs pairs of opposite “conductivity type” or polarity type(P-type & N-type) interconnected to take advantage of theircomplementary nature to operate as a team and with symmetry to self-biasnear the midpoint between power supplies. In addition, the relativeconductance of the first and second channels of the iFETs can beadjusted (threshold choice, relative sizing, and doping profiles) totailor the gain, speed, quiescent current and input impedance of such ancomplementary iFET (or CiFET) compound device of the present invention.

The iFET, with its iPort provides an uncommon and unexpected solution tothe compensation problem, and then continues to provide new oralternative solutions to other old problems, exceeding industryexpectations. The advantages of operating circuits in “weak-inversion”have long been known but, so also have the problems. The CiFET enablescircuits to exploit the high gain and wider dynamic range available in“weak-inversion,” without sacrificing superior speed performance. TheCiFET compound device provides a standard active IC gain device that issuperior to ordinary analog MOSETs making digital ICs host analogfunctionality. It is not a tradeoff.

The following is a list of some of the unusual aspects of a CiFET basedcircuit, including, but not limited to:

-   -   Operates at low power supply voltage;    -   High gain;    -   Extremely linear;    -   Very high speed (wide band);    -   Self-Biasing;    -   Low noise;    -   Quick recovery (DC);    -   Uses all digital parts and processes;    -   iPorts respond to charge (things in nature are charge based)        rather than Volts across a Resistance; and    -   iPort has wide dynamic range with constant gain in an open loop.

Referring to FIGS. 2a and 2b , according to a preferred embodiment ofthe present invention, an iFET 200, is shown which is comprised ofsubstrate 26 a or 26 b, source terminal 24 a or 24 b, and drain terminal29 a or 29 b, defining therebetween two channels 23 a and 25 a, or 23 band 25 b on the substrate 26 a or 26 b, respectively. Typically thefirst (source channel 23 a, or 23 b) is connected to the power supply(not shown) while the second (drain channel 25 a, or 25 b) connects tothe load (not shown in FIG. 2a ). The substrate 26 a or 26 b is N- orP-type. The two channels, source and drain channels 23 a and 25 a, or 23b and 25 b, respectively, are connected to each other as shown in FIGS.2a, and 2b , at the iPort control terminal 21 a or 21 b, and thechannels 23 a and 25 a, or 23 b and 25 b, share a common gate controlterminal 27 a or 27 b, respectively. The soruce channel portion of thegate control terminal s27 a/s27 b is capacitively coupled to the sourcechannel 23 a/23 b; while the drain channel portion of the gate controlterminal d27 a/d27 b is capacitively coupled to the drain channel 25a/25 b. This configuration means that the iFET 200 has more than onecontrol input terminal.

The gate control terminal 27 a or 27 b operates like a conventionalMOSFET insulated gate, with its high input impedance and acharacteristic trans-conductance (g_(m)) transfer function. Typicalvalues of (g_(m)) for a small-signal MOSFET transistor are 1 to 30millisiemens (1 millisiemen=1/1 K-ohm) each, a measure oftrans-conductance.

The iPort control terminal 21 a or 21 b is low impedance with respect tothe source terminal 24 a or 24 b, and has a transfer function that looksmore like beta (β) of a bipolar transistor, but is actuallytrans-resistance (or r_(m)), or more generally, especially at highfrequencies, trans-impedance, measured in K-ohms, where the outputvoltage is a consequence of an input current. Typical resistance values(or values of r_(m)) for a small-signal iFET transistor 200 are 50 KΩ to1 MΩ, a measure of trans-resistance. Current input to voltage output(trans-impedance) is the basis for the assertion that 1 uA in will yieldan output of 100 mV (or a gain of 100,000:1) at a large signal level, or1 pA in will yield an output of 100 nanoV (or a gain of 100,000:1) in anLNA (both results from the same circuit).

These values have been shown to remain true for a single minimum sizedCiFET, with inputs from 1 pico-ampere to 10 micro-amperes, using thesame circuit in simulation and limited device measurements. In 180 nmCMOS construction the noise floor limits measurements below about 10pico amps. iFETS can be constructed with different length to widthproportions with very predictably differing results.

High gain, uncharacteristic or surprising results differing from thestate of the art designs, is the result of the “weak-inversion” likeexponential characteristics of the source channel 23 b of the iFET 200operating in a highly ionized super-saturation mode 28 b.

Speed in this super-saturated source channel 23 b is not limited by thetransit time of carriers along the source channel 23 b, but the highconcentration of ionized charge carriers in the active channel only haveto push the surrounding charge a little as charge is either added orremoved from the source channel 23 b by means of the iPort controlterminal 21 b, resulting in a diffusion current which is defined byexponential relationship as has been realized when a MOSFET is operatedin weak-inversion. This is in contrast to an electric field causing thecharge to transit the channel, which is a square-law function of thegate control voltage. In this configuration, speed is faster than logicbuilt from the same fundamental transistors and unhampered by the“weak-inversion” stage that has higher gains like bipolar transistors.As opposed to bipolar transistors, control current can go either in orout of the iPort control terminal 21 b as well as operate with no iPortcurrent, which is useful for creating a self-bias operating point.

In a self-biased CiFET all of the channels are operated with a higherthan normal gate to channel voltage and a lower than normal voltagegradient along the channel. This provides lower noise which isfacilitated by the self-biasing approach. The potential at drainterminal 29 a or 29 b is the same as potential at the gate controlterminal 27 a or 27 b, greatly reducing the pinch-off effect found inconventional analog circuit designs.

The iFET 200, because of the common gate connection over the sourcechannel 23 a/23 b and drain channel 25 a/25 b, a higher thanconventionally applied voltage is placed on the source channel gatecontrol terminal s27 a/s27 b (or SG) with respect to the source terminal24 a/24 b and source channel 23 a/23 b when compared to the gate voltage17 e used for weak-inversion 13 e of FIGS. 1e and 1f . This higher thanexpected voltage 22 b FIG. 2b is responsible for a much thicker (lowerresistance highly ionized) conduction layer 28 b, allowing themainstream of carriers to avoid the traps in the surface of the crystallattice just under the gate s27 b, hence—much lower noise similar to themanner in which a junction field effect transistor (or j-FET) conductionchannel is located below the surface.

Trans-resistance (r_(m)) is the “dual” of trans-conductance (g_(m)).When looking up trans-resistance, most of the references are toinductors and capacitors, suggesting that the iFET may be useful insynthesizing inductors. Thus ultra-pure sine-wave oscillators can bemade from CiFET stages that do not use inductors.

The iFET works in the following ways: A low noise amplifier requires alow impedance channel. A low impedance channel is low in voltage gainbut high in current gain. To establish voltage gain, a second stage,operating as a current to voltage converter, is required. A cascodedpair (one on top of the other) of transistors provides such aconfiguration. Biasing requirements for a cascoded pair preclude its useat low voltage unless a convenient solution for the biasing problem isfound. The CiFET device structure provides the solution to this problemthrough self-biasing of a complementary pair. The impedance of thesource channel 23 b can be designed to accommodate the impedance of theparticular signal source driving it (see later section on ratio).

Regarding FETs in general, carriers are attracted to the surface by thegate field, a low gate voltage creates a thin surface-layer on thechannel (where the conductivity takes place) while a higher gate voltagecreates a thicker under-layer. The thin layer of carriers is impeded bythe non-uniform surface defects resulting in electrical noise, while athicker layer of carriers finds a smoother path below the surface, thusreducing total electrical noise. This indicates that higher gate voltagetranslates to lower noise.

Referring to FIG. 2b , in the iFET 200 the electric field created by thegate voltage Vg 22 b on the gate control terminal 27 b causes carriersto rise from the substrate 26 b into the source channel 23 b regionconverting the semiconductor material to an ionized conductor with arelatively large number of carriers per volume which is identified as“super-saturation” 28 b, thus establishing a high level of conductivity.

Injection current 20 b introduced into the iPort control terminal 21 bincreases the diffused charge density (number of carriers per volume)throughout the source channel 23 b, thus making the source channel 23 beven more conductive. The rate of conductivity change is exponential,similar to that found in “weak-inversion.” This exponential rate ofconductivity change is due to the low voltage gradient along the sourcechannel 23 b (source terminal 24 b to iPort control terminal 21 bvoltage gradient).

The iFET exponential relationship between source channel 23 b charge 28b and gate voltage 25 b provides access to exponential/logarithmicfunctionality, where the addition of two logarithmic functions isequivalent to multiplication when an antilog is applied. A reversingantilog or exponential operation recovers the analog output through theopposing complementary CiFET loading device structure. This complementis obtained through opposing diffusion types, similar to CMOS logic,instead of some other transistor linear circuit configuration. Suchexponential relationship may be used for various low noise amplifierapplications as well as many analog mathematical operations. Theexponential relationship is also responsible for the wider dynamic rangeof these CiFET circuits.

Again, referring to the source region in FIG. 2b , removing charge fromthe gate control terminal 27 b or/and iPort control terminal 21 b(number of carriers per volume) results in reduced conductivity of thesemiconductor material in the source channel 23 b. In this respect, theiPort control terminal 21 b-to-source terminal 24 b connection operatesin a manner similar to the base-region of a bipolar transistor (which isexponential): the more control current to the iPort control terminal 21b, the more the device conductivity (g_(m) or 1/r_(m)). In addition tothe base current operation of a bipolar transistor, the iPort workssymmetrically around zero injection current in either direction, thus itpossesses true bidirectional operation for four quadrant operations.

The drain channel 25 b of the iFET 200 operates more like a conventionalFET, in that the thickness of the drain channel 25 b is greater near theiPort control terminal 21 b (same thickness as the source channel 23 b)and tapers as it reaches its diffusion region around the drain terminal29 b (the decreasing voltage differential between drain channel 25 b andgate control terminal 27 b diminishes the gate 27 b to channel 25 bfield) establishing the output resistance of the transistor as set bythe gate voltage V_(g). The tapered decreasing channel 25 b depth nearthe drain 29 b is from the lower gate 27 b to drain 29 b voltage whichdecreases the number of carriers that are ionized up from thesemiconductor body 26 b below into the conduction channel 25 b. Whenloaded with a complementary iFET, the resulting CiFET device FIG. 3e isbiased at a lower gate 27 b to drain 29 b voltage (close to the voltagefound on the gate), decreases the drain channel output resistance(thicker channel 25 b at the drain diffusion). This lower drain channelresistance results in lower noise and a high output drive capability toestablish the desired drain voltage at the drain 29 b regardless of thecapacitive load.

A thick source conduction channel 23 b within the iFET 200, operating ata low voltage gradient along this channel, has a low voltage gain but ithas a high power gain as a result of the low input impedance whichefficiently accepts input signal energy from the iPort in the form ofinput current. This source channel also contributes a very minimalnoise.

The conduction region 25 b around the drain terminal 29 b, operating ata higher voltage along its conduction channel 25 b, provides the desiredvoltage gain with a minimal noise contribution when operated with thedrain voltage being the same as the gate voltage V_(g) 27 b. Thisvoltage equality is contributed by a unique biasing construct of theCiFET FIG. 3e , to be explained hereinafter.

FIG. 2b further shows iFET channel charge distributions, according tothe present invention, with their operating points 23 c, 25 c, and 23 d,25 d graphed for a zero iPort injection current FIG. 2c and for amaximum positive iPort injection current FIG. 2d respectively. Verticallines from V_(t) at 27 c/27 d represent threshold voltage in FIGS. 2cand 2d . This threshold voltage is the dividing line between weakinversion and strong inversion. At threshold voltage 50% of the channelcurrent is diffusion driven and 50% is driven by the electric fieldalong the channel, thus below threshold voltage 27 c/27 d the channelcurrent is becoming predominately diffusion driven which possessesexponential characteristics. In super-saturation, the channel isessentially all diffusion driven, thus exponential characteristicsdefine the channel carrier conduction or channel conductance. With zeroiPort injection current at 20 b in FIG. 2b , as shown in FIG. 2c , biascurrent at Id produces the bias point output at 25 c with voltage Vd 29c as it is measured at the drain terminal 29 b, along with an iPort 21 bvoltage at its bias current Id point 23 c.

FIG. 2d illustrates how a small amount of iPort current 20 dimpressively changes the drain channel output voltage to a point at 25d: With a maximum positive iPort 20 b injection current, the ΔId biascurrent from 23 d to 20 d produces the Vd output voltage at 29 d (seenat the drain terminal 29 b), along with an essentially constant iPort 21b voltage at its bias point 23 d. The iPort voltage remained basicallyconstant while the drain voltage changed by nearly half of the powersupply voltage, thus input current changes the output voltage,demonstrating a trans-impedance transfer function. This trans-impedanceoutput voltage 29 b, 29 c, 29 d changes as if the input current isflowing through the trans-impedance r_(m) resistance, while it isactually flowing into the super-saturated source channel, which has aninput resistance that is much lower. The source channel is a current toexponential voltage (at the iPort) converter and the drain channelprovides the anti-log conversion back to form the output drain voltage,while providing all the drive required for various capacitive loads.

The iFET 200 of the present invention can be viewed as a differentialamplifier (or long tailed pair), as shown in FIG. 2e , where drainchannel 25 e converts the “−Voltage” input to the “Voltage DerivedCurrent” and the iPort “+Current” input is a current (rather than avoltage). The source channel 23 e convers “Bias” from negative powervoltage Vss 24 e. A balance is still required between the current input21 e and the voltage derived current from the drain channel 25 e, withthe difference being presented as a voltage change on the outputterminal 29 e. While this output suffers from some non-linear transfercharacteristics, the use of an adaptive load with a complementarynon-linearity compensates, resulting in an ultra-linear transferfunction and can be viewed as a “black box” as shown in FIG. 2 g.

FIG. 2h shows series transistor channel arrangement in the iFET,illustrating the current-voltage arrangements of the two channels 23 hand 25 h which corresponds to 23 b and 25 b of FIG. 2b , producesvoltage V_(out) at 29 h. With zero iPort 21 h injection current, thecurrent through the drain channel 25 h is constrained to be the exactsame current that passes through the source channel 23 h. Withoutleakages or an iPort current, there is nowhere else for the current togo except through the series path of these two channels. If the twoseries transistors in FIG. 2h are sized equally, their gate to channelcontrol voltages want to be the same. That is V_(gi) 27 h wants to bethe same as V_(gs) in FIG. 2h , thus forcing the iPort voltage V_(i) atiPort 21 h to be the same voltage as the source voltage V_(s) at thesource 24 h. This restraint ideally forces low impedance at the iPortinput terminated with zero volts to the source. By altering the relativeconductance ratio of these two channels, the input impedance andtermination voltage can be set. Since both transistor channels are madetogether and adjacent to each other, the input impedance and terminationvoltage are a very fixed and consistent pair of parameters, similar tomatching of a differential pair of transistors. Their bandgaprelationship configuration is a PTAT for the N channel iFET (Vittoz,Eric A. et al., “A Low-Voltage CMOS Bandgap Reference”, IEEE Journal ofSolid-State Circuits, Vol. SC-14, No. 3, June 1979, at page 573 to 577)and a CTAT reference for a P channel iFET (Anvesha A, et al., “A Sub-1V32 nA Process, Voltage and Temperature Invariant Voltage ReferenceCircuit”, 2013 26^(th) International Conference on VLSI Design and the12^(th) International Conference on Embedded Systems, IEEE ComputerSociety, 2013).

FIG. 2i illustrates a slightly higher level circuit prospective of theiFET operation, which exemplifies a trans-resistance transfer function.Here an input current to a virtual PTAT reference voltage provides anoutput voltage change that is multiplied by the trans-resistance r_(m)and strongly buffered. This trans-resistance r_(m) gain ratio istypically in the range of 50K to 2 Meg.

FIG. 2j is a behavioral schematic of the iFET operational model whichillustrates the iFET behavioral relationship in a more detailedschematic. The I_(inj) current into the iPort sees a low R_(in) to aPTAT voltage above V_(s) at the iPort input. At the output this I_(inj)current input becomes a voltage that has a magnitude that looks like itwent through a high resistor r_(m), but is sourced at the output V_(out)with a low impedance variable output voltage source. This low impedancecan equally drive highly varying capacitive loads as normallyencountered in integrated circuit instantiations. This functionality isdepicted with FIG. 2g at the “black box” level where a current inputproduces an r_(m) times higher V_(out). This black box depiction of atrans-resistance amplifier is the dual of the normal MOS amplifierdepicted in FIG. 2f where an input voltage produces an output currentthat is the input voltage multiplied by g_(m). It is highly desirable toprovide a voltage output instead of a current output that must be turnedback into a voltage by running this current into a load resistance. Theload significantly effects the voltage in the g_(m) amplification blackbox while it does not in the r_(m) black box amplifier.

FIGS. 2k and 2L are suggested schematic symbol for the iFET device.

FIG. 2m captures yet another application of the iFET 200, which providesa methodology of obtaining a voltage output from a bi-directionalcurrent input on the iPort. This follows a trans-impedance r_(m)transfer-function which is precisely defined over an extremely widedynamic range FIG. 3h . At this iPort terminal 21 m, a bi-directionalinput current into an iFET 23 m provides a proportionally large voltagechange on the output 29 m which is biased with a load current 28 m. Thisoperates through the weak-inversion like exponential characteristic ofthe iFET source channel 23 b as shown in FIG. 2b by altering the amountof charge in the super-saturated 28 b source channel of the iFET 200.The gate is provided with bias voltage, V_(bias) 27 m. Thistrans-impedance r_(m) transfer-function is set by the relativeconductance ratio of the iFET source channel 23 b to drain channel 25 bas plotted in FIG. 3i . Here the conductance ratio is plotted alongthe-axis and the trans-resistance r_(m) or more generally, thetrans-impedance is plotted up the right axis. This plot 3 i also plotsthe directly related iPort input resistance on the left axis.

Non-Inverting Nature

Regarding the iPort control terminal 21 b as shown in FIG. 2b , in thecase of an N-channel device, a positive current 20 b on the iPortcontrol terminal 21 b, such an input displaces the current coming inthrough the upper channel 25 b, causing the drain (output) connection 29b to move in a positive direction—thus the non-Inverting nature of theiPort 21 b input.

Interestingly, unlike other semiconductor devices, a negative current 20b can be extracted from the iPort 21 b, causing a drain (output) 29 bshift in the negative direction.

Proper Bias

An iFET 200 (as shown in FIGS. 2a, 2b ) has both gates 27 a, 27 bconnected together and requires a proper bias voltage 22 b on the gate27 a, 27 b to establish the desired operating point.

Symmetry

A P-channel device can be constructed and behaves in a similar fashionto its N-channel counterpart.

It should be emphasized that while the gate input 27 a, 27 b is invertedwith respect to the drain, the iPort 21 a, 21 b is NOT inverted inEITHER the PiFET or NiFET devices diffusion types with respect to theiroutput drains.

The “Rule-of-Thumb” View:

Referring to FIG. 2d or 2 j, the operation of the iFET transistor isextremely simple to think about; not much more than Ohm's law is needed,and it can be seen as followings:

-   -   A small + or − current input on the iPort results in a voltage        out that is “K” times larger, but with the same sign as the        input.        -   1. “K” does not change over an enormous dynamic range of            operation.        -   2. “K” is on the order of 100,000, defined as            trans-resistance (r_(m)) and can be viewed as a simple            functional block shown in FIG. 2g . r_(m) units are ohms            which is V_(out)/I_(in). r_(m) of FIG. 2g represents the            transfer function of the iPort control terminal of an iFET            in accordance with the present invention.        -   3. The r_(m) block in FIG. 2g is the “dual” of the g^(m)            block in FIG. 2f , which defines the normal MOSFET transfer            function. Accordingly, current and voltage have been            interchanged, and thus r_(m) as shown in FIG. 2g can be            viewed as a simple resistance in ohms, while g_(m) as shown            in FIG. 2f is conductance in units of 1/ohms.

The r_(m) circuit of FIG. 2g has low impedance on both the input andoutput while the g_(m) circuit of FIG. 2f has high impedance on both theinput and output. The benefits of the r_(m) iFET circuit of FIG. 2g areessentially zero voltage swing at the input and all the output currentdrive required to establish the output voltage, yielding parasiticcapacitance insensitivity on both the input and output, thus very highspeed. The resulting r_(m) circuit of FIG. 2g through 2j is essentiallyconstant with frequency and operates with much lower power supplyvoltages than the g_(m) circuit of FIG. 2f , in that the trans-impedancer_(m) iFET device's operation is basically not threshold voltagelimited. The power supply voltage does not stop at the sum of thresholdvoltages or a threshold voltage and a saturation voltage as in prior artanalog circuits, but functions well below 600 mv and operates usefullydown to a millivolt of power supply voltage. Gain typically hits itsmaximum in the range of 600 mv to 1.0 volt of power supply voltage.Clearly not threshold voltage limited. Many of the iFET benefits areworth the trouble of re-thinking the approach to analog MOS circuitdesign.

The useful power gain is partially realized as current gain. AlthoughMOS circuits are perceived as voltage mode circuits, analog MOS circuitswork much better as current or charge controlled circuits. After all MOStransistors operate on the instantaneous charge in their channels and doso with great precision as seen throughout this specification.

-   -   The iPort input terminates in a non-varying, low value        resistance (typically 50Ω-50 kΩ depending on design). The        circuit allows matching an antenna impedance for maximum power        transfer into the iPort input.    -   The output is a voltage source with a low driving impedance,        providing the load with whatever current is required to        establish the desired voltage with precision.        Additional iFET observations of the present invention are as        follows:    -   r_(m) does not change over the entire operating range from near        clipping, all the way down to the noise floor. AC performance of        an iFET is FLAT from DC to faster than logic speed. Analog        voltages only move a little while logic has to get unstuck from        one rail and go all the way to the other power supply rail.    -   The iPort control terminal, being a current input, is free of        voltage derived parasitic effects because the iPort control        terminal has very minimal voltage change.    -   FIG. 3k shows the input termination voltage at iPort control        terminal from ½ mv to about 100 mv, depending on the iFET ratio        (or input impedance), from its respective power supply rail,        allowing a high compliance voltage from the other rail to bias        the input such as desirable for transducer or some other input        circuit.    -   The iPort termination voltages are either a PTAT or a CTAT        (proportional to absolute temperature or the complementary to        absolute temperature) bandgap reference depending on the N or P        semiconductor diffusion type respectively.    -   The output in the complementary CiFET configuration swings        around the self-bias midway voltage (“sweet-spot”) between the        power supply rails, where it is free of power supply induced        noise. Power supply induced noise cancels with this “sweet-spot”        as the analog-zero reference.    -   The advantages of operating circuits in “weak-inversion” have        long been known but, so also have the problems. The iFET enables        circuits to exploit the high gain and wide dynamic range        available in “weak-inversion,” without sacrificing superior        speed performance.    -   In the “Behavioral Model” FIG. 2j the iPort current is converted        to a voltage by a resistance (r_(m)), whose value determines the        gain. This “trans-resistance” (r_(m)) is established by the        ratio of the “drain channel” to “source channel” conductance,        and remains constant throughout the entire operational range.        Simulation has shown this resistance (r_(m)) to typically be in        the range of 100,000Ω, set by the relative channel sizing. r_(m)        is the dual of g_(m), but with more control.        -   a. The output is a low-impedance source follower that can            deliver its voltage with all the necessary transient current            to drive the next circuit and capacitive load to get there.        -   b. The input is a constant low resistance termination            (related to r_(m) but much lower) with a constant            termination voltage of about 100 mv from the respective            power supply rail. This offset voltage is a “bandgap”            reference, established by the ratio of the “drain channel”            to “source channel” conductance.            The CiFET Amplifier is the Basic Analog-in-DIGITAL Building            Block:

The complementary nature of a CMOS inverter of FIG. 1i is of interestfor processing analog signals. If the inverter output is tied back toits input, it self-biases near the midpoint of power supply voltage.Care, of course, must be taken to size the individual transistors weaklyenough as to not exceed what the IC process can handle, such as maximumcurrent the contacts are rated for in both their AC and DC ratings.Local temperature rise is also a consideration, but self-biasing combatstemperature degradation.

When sized with similar pull-up conductance to pull-down conductance,the self-bias point is nicely centralized between the power supplieswhere noise from both the positive and negative power supplies tend tocancel. The variation in process parameters will move this midpointvoltage around a bit, but it is always relative the transistorconductance ratios. At this midpoint, the gain is arguably at themaximum available for the pair of transistors used. In addition, thepull-up performance is equal to the pull-down conductance yieldingsymmetric DC, AC, and transient response in either direction. Theeffective threshold voltages cancel each other out in that the circuitalways works at its best. The AC bandwidth performance of thisconventional inverter is extremely wide as compared to any analogcircuit configuration as illustrated in the Bode Plot of AC Gain andPhase in FIG. 3u . You get the most bang for the least amount ofparasitic loading. For the 180 nm IC process used as a comparisonbaseline, the 3 db gain is about 1.2 GHz with a phase shift of about 45degrees from DC. One would be hard pressed to run equivalent low powerlogic at 1 GHZ in the 180 nm reference technology using a minimum powerlogic family.

A primary limiting factor to the use of a logic inverter for an analogvoltage amplifier is that the logic inverter has only about 25 db or 18×of voltage gain available with a single inverter stage, as illustratedin the standardized Bode gain-phase plot of FIG. 3u . The requiredminimum analog voltage gain has to be at least 80 db or 10,000×. Thevoltage gain defines how well the analog output signals reach theirdesired amplitude.

Closed loop analog voltage amplifiers require inverting gain so that theoutput feedback can move the input back to a virtual ground inputvoltage. Without the amplifier being inverting, the positive feedbackwould result in a latched output, like a flip-flop when the feedbackloop is closed. Using a series of say three inverters is virtuallyimpossible to stabilize with any frequency response left over in aclosed loop application, which is essential for practical analogamplifiers.

While a single iFET has interesting characteristics on its own, acomplementary pair of iFETs prove to be much more beneficial. Theresulting device is arguably the highest possible power gain and widestbandwidth use of FETs possible. FIG. 3a is the schematic diagram of sucha complementary pair of iFETs herein named CiFET for complementarycurrent input field effect transistors. This is the core of the presentinvention.

FIGS. 3b and 3c structurally relate the CiFET transistor 300 schematicdiagram of FIG. 3b to the adjacent physical layout abstraction of FIG.3c . The NiPort 31 b of the NiFET transistor 301 in FIG. 3b relates tothe NiPort 31 c in the physical layout abstraction of FIG. 3c . ThePiPort 32 b of the PiFET transistor 302 relates to PiPort 32 c in FIG.3c . The reference numbers cross relate the transistor schematic to thephysical layout. Likewise, these reference numerals also cross referenceto the 3-dimensional sketch of FIG. 3d and the cross section AA view ofFIG. 3e . This set of CiFET FIGS. 3a through 3e and theircross-reference relationship is a reflection of the prior art 2-fingerinverter of FIGS. 1i to 1 n.

Essentially, the two pairs of opposite diffusion type transistors 101and 102 in the inverter device structure 100 FIG. 1m , and again in FIG.1n , are each connected in parallel: 13 m in parallel with 15 m as wellas 14 m in parallel with 16 m for the 2-finger inverter 100. These twopairs of parallel transistors are also connected to the output terminal19 m with the cross-hatched metal connection 18 m, or equivalentlyshaded portion 18 k in FIG. 1k or 18 n bold wire in FIG. 1 n.

These same two pairs of transistors 33 d, 35 d (or 33 e, 35 e) and 34 d,36 d (34 e, 36 e) are connected in series in FIGS. 3d and 3e in order toform their respective iFET device structures 301 and 302 thus formingthe CiFET device structure 300 with their respective iPort controlterminals Ni, Pi access using the intermediate diffusions 31 d, 32 d.Just a metal mask modification from the connections 18 k, 18 m, 18 n inFIGS. 1k, 1m, 1n to the connections 38 d, 38 e in FIGS. 3d and 3e ,respectively, yields unprecedented analog performance as is presented inthe remaining figures of this present invention. Thus CiFET designs arecompletely compatible, and portable, to any IC process of which allpossess their most fundamental logic inverter; while being a radicalimprovement from the state of the art in high gain, high precision, andsmall scale primitive analog building blocks. The complementary pairs ofiFETs are built entirely from logic components, without analogextensions, while enabling scaling and portability. Both the footprintand the power consumption per gain/bandwidth are drastically reducedfrom the present state of the art, while retaining superior noiseperformance.

Referring to FIG. 3a , the complementary pair of iFETs (or CiFET) 300comprises P-type iFET (or PiFET) 302 and N-type iFET (or NiFET) 301,comprising input terminal 30 a connected to both the gate controlterminal of PiFET 302 and the gate control terminal of NiFET 301,function as the common gate terminal 30 a. CiFET 300 receives power,Power+ (or positive supply voltage) and Power− (or negative supplyvoltage), where Power− is connected to the source terminal of NiFET 301and Power+ is connected to the source terminal of PiFET 302. Each ofPiFET 302 and NiFET 301 comprises iPort control terminal (31 a and 32 a)for receiving injection current. The drain terminal of PiFET 302 andNiFET 301 are combined to provide output 39 a.

Referring to FIG. 3d (or FIGS. 3c, 3e ), the CiFET 300 comprising PiFET302 and NiFET 301, laid out on the substrate (or body B+ and B−respectively) like a mirror image along well border shown therein. PiFET302 comprises source terminal S+ s34 d (or s34 c, s34 e), drain terminalD+ d36 d (or d36 c, d36 e), and iPort control terminal Pi, definingsource+channel 34 d (or 34 c, 34 e) Between the source terminal S+ andthe iPort control terminal Pi diffusion region 32 d (or 32 c, 32 e, or32 b in FIG. 3b ), and drain+channel 36 d (or 36 c, 36 e) between thedrain terminal D+ and the iPort control terminal Pi diffusion region 32d (or 32 c, 32 e, or 32 b in FIG. 3b ); NiFET 301 also comprises sourceterminal S− s33 d (or s33 c, s33 e), drain terminal D− d35 d (or d35 c,d35 e), and iPort control terminal Ni, defining source−channel 33 d (or33 c, 33 e) between source−terminal S− s33 d (or s33 c, s33 e) and theiPort control terminal Ni diffusion region 31 d (or 31 c, 31 e, or 31 bin FIG. 3b ), and drain−channel 35 d (or 35 c, 35 e) betweendrain−terminal D− d35 d (or d35 c, d35 e) and the iPort control terminalNi diffusion region 31 d (or 31 c, 31 e, or −b in FIG. 3b ). CiFET 300further comprises a common gate terminal 30 d (or 30 c, 30 e, or 30 b inFIG. 3b ) over source+channel 34 d (or 34 c, 34 e), drain+channel 36 d(or 36 c, 36 e), source−channel 33 d (or 33 c, 33 e), and drain−channel35 d (or 35 c, 35 e). Accordingly, the common gate terminal 30 d (or 30a, 30 b, 30 c, 30 e) is electrically coupled to the iPort controlterminals Pi and Ni.

In many analog circuits, biasing is a problem. Using iFETs incomplementary pairs 301 and 302 as shown in FIG. 3d allows them to“self-bias” when the drain output 39 d (or 39 a, 39 b, 39 c, 39 e) isconnected to the gate input 30 d (or 30 a, 30 b, 30 c, 30 e), thuseliminating drift problems and additionally, the amplifier finds themaximum gain point on its operating curve. This self-bias connection isillustrated in FIGS. 3f and 3g as 38 f, 38 g and also in FIG. 3L as“Bias” for an analog zero reference.

In the “Behavioral Model” of CiFET of the present invention as shown inFIG. 3f , the currents I_(inj) at the iPort control terminals 31 f and32 f are converted to a voltage by trans-resistance (r_(m)), whose valuedetermines the gain. This “trans-resistance” (r_(m)) is established bythe ratio of the “drain channel” to “source channel” conductance, andremains constant throughout the entire operational range. Simulation hasshown this resistance (r_(m)) to typically be in the range of 100,000Ω,set by the relative channel sizing. r_(m) in Ω is the dual of g_(m)(1/Ω).

The output V_(output) 39 f is a low-impedance source follower that candeliver its voltage with all the necessary current to drive the nextcircuit and any capacitive loading in between. The common gate inputterminals 30 f/30 g represent the common gate input terminals 30 a/30b/30 c/30 d/30 e of their previous related FIGS. 3a /3 b/3 c/3 d/3 e.The CiFET structurally differs only in the output 39 a/39 b/39 c/39 d/39e metal connection 38 c/38 d/38 e from that of the two finger inverterof FIGS. 1i /1 j/1 k/1 m/1 n output 19 i/19 j/19 k/19 m/19 n metalhookup 18 k/18 m/18 n. The CiFET is only a metal connection differencefrom the two-finger inverter, and can be further optimized by adjustingthe individual transistor conductance for the intended CiFET purpose.Only a couple of optimizations are required for most purposes.

The input is a constant low resistance termination (related to r_(m) butmuch lower) with a constant offset voltage of about 100 mv from therespective power supply rail. This offset voltage is a PTAT/CTAT“bandgap” reference, established by the ratio of the “drain channel” to“source channel” conductance.

A standard CiFET compound device cell can be physically constructed andused like a logic cell for designing analog. Normally this is the onlyactive circuit component needed for analog circuits. Like a transistor,but the CiFET cell does everything needed for an active component.

Now, referring to FIG. 3g , V_(input) 30 g is connected to the gateterminals of NiFET and PiFET. Positive power voltage (Power+) isconnected the source terminal of PiFET, while negative power voltage(Power−) is connected to the source terminal of NiFET. NiFET providesthe channel 33 g and PiFET provides the channel 34 g. NiFET furthercomprises NiPort 31 g; while PiFET compries PiPort 32 g. Drain terminalsof NiFET and PiFET are connected together to form V_(output) 39 g.Self-Bias path 38 g is provided from V_(output) 39 g to V_(input) 30 gfor repeatability.

How then is the proper bias voltage produced? The simplest way ofgenerating the bias voltage is to use iFETs in complementary pairs 301and 302, creating an inverting device 300 as shown in FIGS. 3d and 3L,and then using the output 39 d to provide negative feedback “Bias”connection in FIG. 3L to the input 30 d. The CiFET as a compound devicewill “self-bias” at a point approximately midway between the powersupplies, where the gain is maximized and the speed or slew rate issymmetrically poised for its most rapid changes. At this self-biasvoltage point, the current through all of the complementary iFETchannels 33 d, 35 d, 36 d, 34 d is exactly the same current, thus equal.There is no other DC current path for the PiFET 302 drain d36 d to gothrough except into the NiFET 301 drain d35 d, and thus a specific setof gate to channel voltages within the CiFET conduction channels areestablished for this equality of currents (or conductivity). Also sinceboth iFETs 301 and 302 have the same current, the pull-up ability isexactly equal to the pull-down ability, which defines the maximum slewrate bias point.

Since the complementary pair 300 of iFETs 301 and 302 is self-biased,any parametric factors are auto-compensated for changes in operatingenvironment. Because of inherent matching between adjacent parts on anIC, the bias generator can be used to bias other iFETs nearby. Thereal-time self-biasing circuit corrects for parametric changes (invarious forms).

Each of the transistors in an inverter of the present invention acts asa “dynamic” load for its complement, allowing the gate voltage to besignificantly higher than the traditional bias point of an analogcircuit gate. With the complementary iFET compound device's higher thannormal gate voltage, the source and drain conduction channels are deep,yielding lower noise.

The dominant noise source in a traditional analog circuit is primarilyrelated to the “pinch-off” region near the drain 19 g of the conductionchannel 15 g illustrated in FIG. 1g . The length of this pinch-offregion is effected by the magnitude of the drain to source voltage.Biasing the Drain 19 g, 29 b FIGS. 1g, 2b (or output) at the samevoltage as the gate 17 g, 27 b (zero differential) causes the drainconduction channel to avoid the channel pinch-off (shallow channel)phenomena usually encountered in analog circuits. Another way of statingthis is: a transistor gets noisier as the drain approaches its designmaximum voltage, the self-biased inverter operates its transistors athalf the design maximum voltage and the gate is at the same voltage asthe drain (zero differential), therefore the self-biased inverter ismuch quieter. With lower drain voltage, the ionized conduction channelcarriers diffused down away from the surface carrier traps which arejust below their gate.

The operation of the CiFET amplifier differs from the operation of aconventional analog amplifier, with its current mirror loads, in that:

The “Source” channel, as illustrated in the individual iFET FIG. 2b ,has an extremely small (˜100 mv) voltage from source terminal 24 b toiPort control terminal 21 b while the gate terminal 27 b is at ˜½Vsupply when complementary diffusion type iFETS 301, 302 are combinedinto a single CiFET device structure 300 FIG. 3d . This puts the iFETSource channel 23 b, 33 d, 34 d into “Super-Saturation” 28 b, acondition similar to weak-inversion 18 e FIG. 1e but with high gateoverdrive. Gate overdrive results in an unusually thick conduction layer23 b and along with a low source 24 b to iPort 21 b voltage resulting inthat conduction layer 23 b remaining thick and deep all the way alongthe channel. Notice the differences in the thickness between theweak-inversion 18 e conduction channel 13 e in FIG. 1e and thesuper-saturated 28 b conduction channel 23 b in FIG. 2b . This thickchannel difference is why the iFET operates so well. It takes thedesired exponential property of the conduction channel found inweak-inversion 18 e and fixes its high resistance limitation to a verylow resistance conduction channel, with the same exponentialproperties—a long wished for FET transistor performance metric.

The “Drain” channel 25 b operates with its' Drain terminal 29 b at ˜½Vmax, greatly reducing the pinch-off (and DIBBL) effect. This reducedpinch-off condition is further enhanced by the fact that the “Gateterminal” 27 b is operated at ˜½ Vsupply (same as 1/2 Vmax), meaning nopotential difference between the Drain 29 b and the Gate 27 b. Noticethe difference in the thickness between the drain conduction channel 15g in FIG. 1g and that of 25 b in FIG. 2 b.

Another important aspect of the iFET and CiFET compound device is its˜constant voltage low impedance current input 20 b FIG. 2b that frees itfrom the speed robing effects of parasitic capacitance. With currentinput, the input voltage remains nearly constant, thus parasiticcapacitance has little effect on input signal level changes.

This subtle but significant difference is one of the enabling featuresthat makes weak-inversion like exponential response work and gives thecomplementary iFET amplifier its linear response, superior low noise,wider dynamic range, and speed advantages.

MOSFETs do not make particularly good amplifiers compared to equivalentbipolar circuits. They have limited gain, they are noisy, and their highimpedance makes them slow. Process parameters are also soft, so thatmatching a differential input is difficult, unlike bipolar. BipolarDiff-Amps are developed to the point where the input offset is prettygood, but the move to CMOS never really delivered as good a solution.

It has long been known that superior gain and wide dynamic rangeperformance can be obtained from CMOS operated in weak-inversion. Butcomplications arising from high impedance, due to impractically lowcurrents and high output resistance, preclude taking advantage of thesuperior gain (equivalent to that of bipolar transistors), dynamic range(exceeding that of bipolar transistors), and logarithmic performance(allowing numerous decades of amplification) that are characteristic ofweak-inversion. However, the CiFET conduction channels circumvent thesehigh-impedance limitations of weak-inversion due to the CiFET's deepconduction channels 33 d, 36 d, 33 e, 36 e FIGS. 3d, 3e respectively.The CiFET is a low-impedance device that also incorporates the noisebenefits of majority carriers in a deep channel found in junction-FETsto the MOSFET. Improved signal to noise ratios are essential for analogsystem operation with sub 1 volt power supplies of ultra-deep sub-μm ICsystems. When signals are reduced, the noise must at least beproportionally reduced to maintain the signal to ratio. Systemperformance is all about s/n ratio in the end.

While a MOSFET in weak-inversion, working into a current source load,delivers a logarithmic transfer function, the same MOSFET working intoan anti-log load cancels the logarithmic nonlinearity, yielding aprecisely linear transfer function. The CiFET amplifier is such acircuit, i.e.: log input, antilog load, yielding perfectly linear, widedynamic range, low noise, and high speed performance. The low noise is aconsequence of the biasing, where the source channel gate potential isunusually high and the potential across the source channel itself ismaintained at near zero volts while the voltage across the drain channelis minimized. The drain channel is a level shifter, maintaining a verylow voltage on the source channel while delivering high amplitude signalswings at the output with all the output drive to charge any capacitiveload. The CiFET is a trans-impedance amplifier FIGS. 2g through 2j and3f , which is a low-impedance device. The prior art trans-conductanceamplifiers FIG. 2f are high-impedance devices. Low-impedance devicesgenerally have low noise, while high-impedance devices have high noise.

A 3-stage CiFET voltage amplifier delivers an open loop voltage gainof >1 million or 10⁶ which is 120 db and equivalent to 20 bits ofdigital accuracy, while still maintaining unity gain closed loopstability over its multi-GHz bandwidth. At power supply voltages below 1volt gains can easily be around 100 million or 10⁸ which is 160 db andequivalent to 27 bits of digital accuracy, while still maintaining unitygain closed-loop stability over its GHz bandwidth, which is obviouslylimited by the noise floor. It is all about signal to noise. Gainincreases as power supply voltage is dropped well below a volt. At apower supply voltage of only 10 millivolts, CiFET current inputamplifiers operate with 10 db gain and closed-loop bandwidth over 1 KHz,and can operate at power supply voltages as low as 1.0 millivolt withreasonable performance. Clearly, the CiFET amplifiers are not slaved tothe threshold voltage stacking that prior art amplifiers are.

Taking Advantage of the Doping Profile and Ratioing:

Traditionally engineers have avoided using digital logic in an analogconfiguration because it was believed to be unacceptably nonlinear andwas difficult to bias and impossible to stabilize. Digital logic alsosacrifices drive symmetry for compactness. Restoring the symmetrythrough proper device ratioing (˜3:1 p:n width to ˜4:1 on smaller ICprocesses) improves linearity, increases noise immunity, and maximizesdynamic range. Self-biasing solves the bias problem.

Noise figures can be particularly optimized on front end amplifiersthrough proper ratioing. The iFET's electrical characteristics can beenhanced by modifying the combined and relative conductance of thesource and drain channels, without modifying the available IC process(without analog extensions). When all the transistors must be the samesize as in the newest IC processes, multiple transistors can be wiredtogether to achieve the desired iFET rationing, as course resolutionworks fine. There are several approaches to realizing this optimization(adjusting length, width, and threshold among others).

Nearly any source and drain channel size will make a functional iFET,but varying the individual iFET channel size, both relative andcumulative, increases the iFET performance depending on the objective.

Fundamentally:

-   -   Lower iPort input impedance is obtained via a lower source        channel current density (wider source channel) as compared to        the drain channel.    -   Higher output voltage gain is obtained via higher source channel        current density (narrower source channel) as compared to the        drain channel.    -   Proportionally sizing the CiFET channel interrelationships        optimizes various performance metrics. Gain and symmetry are        maximized when the P-channel iFET conductance to N-channel iFET        conductance is equalized, thus balancing the CiFET complementary        conductance. Equalizing conductance adjusts the self-bias        voltage near the midpoint of the power supply voltage. This        provides a symmetrical dynamic analog signal range and serves a        convenient analog ground or zero reference, permitting “four        quadrant” mathematical operations. Experience with deep sub-μm        IC processes place the P-channel iFET to be around 3 to 4 times        wider than N-channel iFET, as fixed by length or width ratios of        the iFET channels.    -   The CiFET performance is minimally affected by ambient and IC        process parameter variation because of self-biasing to an        optimum mid-point, regardless of conditions.    -   The power verses speed tradeoff is controlled by the cumulative        sum of all of the channel conductances used to set the idle        current through the complementary iFET amplifier. This        establishes the output slew rate (or output drive capability).    -   Care must be exercised so as to not exceed both DC and transient        current limitations of the biased CiFET structure. Current        rating for the contacts and metal widths must be considered in        determining the self-bias current and physical layout care must        be considered so as to not be prone to premature failure. Local        heating should also be considered.    -   Since any logic inverter would work, it is not necessary to even        make this optimization, but it is a performance booster.

To be clear, the conductance of the iFET channels are a function of theindividual channel width and lengths, as well as their thresholds anddoping profiles. Each of the iFET channels can have individuallyselected sizes and/or threshold relationships to the other relatedchannels.

While iFET amplifiers can be constructed with minimum sized deviceswhich do provide ample current at the output for very fast response andhigh accuracy, as stated above, care must be exercised so that thecomplementary iFET amplifier does not pass too much current, subjectingit to mechanical failure. The physical layout requires enough contactsand metal for the required DC and transient currents.

Performance Description:

FIGS. 3h to 3t exemplify performance of the CiFET device structure.

FIG. 3h is a transfer function plot of the CiFET device over an extremerange of ±1 pico-amp to ±5 micro-amps of input current into eitheriPort, yielding a ±100 nano-volt to ±500 milli-volt output on thevertical scale. In order to cover the range, both axis are log scale.

-   -   The CiFET is ratioed to provide a r_(m) gain of 100K;    -   Gain remains constant over the entire range;    -   Transfer function is precisely linear;    -   Plus and minus precisely overlay each other;    -   Either iPort input/output precisely overlays the other;    -   Input current can be zero;    -   Output voltage swings around the midscale AC zero reference        voltage,

FIG. 3i shows how the iFET channel conductance ratio defines thetrans-resistance (also known as trans-impedance indicating the same ACrelationship) r_(m) to set the CiFET device gain in which input currentproducing an output voltage. The iFET Ratio is along the horizontal axisas the ratio of width/length of the source channel divided by thewidth/length of the drain channel. The gain factor or trans-resistanceis the right vertical axis in the units of Ωs using a log scale to coverthe 3 decade range of values from about 1 KΩ to 1 megΩ

Also note that the iPort input resistance on the left vertical scale ofthe graph shown in FIG. 3i provides a precisely overlaying plot with areduced set of values by the ratio shown on the following FIG. 3j ,which is related to the peak voltage gain of the CiFET device. In otherwords, R_(m) times the CiFET voltage gain yields the trans-resistancer_(m).

The following FIG. 3k of this CiFET property set plots the iPorttermination voltage over the same iFET ratio on the horizontal scale.Again, the complementary iPorts overlay each other. The scales arealigned with a match of the CiFET ratios. In reality, the N channeliPort termination voltage is a PTAT bandgap reference which has itsvoltage set by the iFET channel ratio relationship. The p Channel iPortis a precise complement CTAT bandgap voltage reference. When these twovoltage references are added the temperature effect of the PTAT cancelsthe temperature dependence of the CTAT yielding temperature independentreference. Their slope offsets can be matched by the matching if theCiFET ratios and also be fine-tuned with a trim current injected intoeither iPort input.

FIG. 3L is the transistor schematic of the CiFET used to generate thesePTAT and CTAT bandgap references. The NiFET Q31L provides the PTATreference on its iPort 31L and the PiFET Q32L provides the CTATreference on its iPort 32L. This CiFET device also provides the analogzero bias reference on its output 30L.

The precise linearity of the temperature relationship over an extremelywide temperature range of −150 to +250 degrees Centigrade is plotted inFIG. 3m . Note the total linearity. The negative or CTAT output on thePiPort overlays the CTAT when the sign is inverted. This graph suggeststhe usefulness in measuring temperature over extended temperaturelimits. The temperature sensitivity is set by the iFET ratio selectionshown in FIG. 3k . A CiFET device can be tethered on a 3 wire line tosense temperature in hostile environments. This works well because theimpedance of the CiFET tethered on the line would be low to minimizenoise pickup.

The AC gain and phase performance of the CiFET device is illustrated bya standardized Bode plot in FIG. 3n for a 75Ω iPort input resistanceCiFET device, and in FIG. 3r for a 35 KΩ (n CiFET device, with the Bodeplot for a minimum sized CMOS 2-finger inverter of FIG. 1i in FIG. 3uand the reference CMOS amplifier of FIG. 1a Bode plot in FIG. 1b forcomparison of all device AC properties. All Bode plot scales are thesame, frequency from 0.1 Hz to 1.0 THz is the horizontal frequency axisusing a log scale, gain is in dB on the vertical scale along with phasein degrees. Both gain and phase scales were set to the same set ofnumbers of 0 d to 180 d. The gain is the thick black line with dashedcross-hairs at the 3 db roll-off point and dotted cross-hairs at thegain cutoff frequency to provide the phase-margin on the phase traceshown as large grey square dots. There are several horizontal lines toidentify gain and phase shifts. The upper dot-dash horizontal line isfor a 45 degree phase shift form DC which is used to target the 3 dbgain roll-off point with the dashed cross-hairs. The next grey dashedreference level is at 90 degrees followed by the dot-dot-dash line at 30degrees to indicate a minimum acceptable phase-margin. The lowerreference line is indicated by small square dots overlaying a thinnersolid line to indicate the zero crossover of both gain and phase. Thishelps compare these three Bode plots to each other.

Following these three Bode plots are three plots FIGS. 3p, 3s, 3v of thechange in voltage gain over power supply voltage so that this propertycan be compared to the CMOS amplifier of FIG. 1a with its comparisonplot in FIG. 1c . These four plots show the voltage gain as the powersupply voltage is decreased in −100 milli-volt steps. The full powersupply voltage for the standardized 180 nm CMOS process is 1.8 volts andis shown as a solid thick black line which is the widest bandwidth inall example plots. Form this thick black trace, the power supply stepsdown by a tenth of a volt in the next 7 various dot-dash combinationgrey traces to the thick dashed plot at a power supply of 1.0 volts. Thenext solid grey traces are steps from 0.9 to 0.6 volts on the powersupply, followed by thin dotted traces going from 0.5 volts to 0.1 voltson the power supply. These plots show that the gain for these circuitsactually goes up as power supply is reduced, with the exception of theprior art CMOS amplifier of FIGS. 1a, 1c which falls off the cliff aspower supply voltage is reduced. The thin dotted cross-hair lines are onthe gain at full power supply voltage and the dashed cross-hair lines isfor the 1.0 volt power supply voltage.

To make this set of plots easer to comprehend, additional graphs followeach plot in FIGS. 1d, 2q, 3t, 3w . These graphs relate gain and cutofffrequency to the power supply reduction. All plots have the same scalesand axis variables. It can be clearly seen that the gain increases aspower supply voltage is reduced. The speed or bandwidth penalty can beeasily visualized with these plots. Typically bandwidth holds acceptablydown to about 0.8 volts of power while gain significantly increasessteadily as the power voltage is dropped down to below to about a half avolt. This is because the channels use a higher percentage ofweak-inversion like diffusion current as power supply voltage is forceddown. It should also be noted that the inverter also increases gain aspower is reduced, for the same forced exponential mode operation pointof the channels.

FIG. 3q shows voltage gain and cutoff frequency as a function of powersupply voltage for 75 ohm iPort CiFET device.

It has been observed in FIG. 2b that the source channel 23 b operates ina “Super-Saturated” mode 28 b which possess exponential propertiessimilar to weak-inversion or bipolar Beta. This mode of operation is notlimited through the conventional FET threshold voltage, but ratherfunctions with higher gain as the voltages are forced well below theconventional threshold voltage. This is because the channels are beingpushed well down into their diffusion mode of operation. Here a chargeinjection provides additional carriers in the channel which enables anincrease in current flow through the channel. This bodes well with FETtransistors because field effect transistors are fundamentally chargecontrolled devices.

This increase in gain with diminishing power supply voltage boostsweak-inversion like operation, where the charge-transport mechanismproduces a higher exponential-class of gain. This is also demonstratedwith the conventional CMOS inverter of FIG. 1i as shown by the standardAC performance plots of FIGS. 3u to 3w . Thus there is a methodology ofobtaining higher gain with lower power supplies that, when recognized,is an alternative to analog circuits being threshold voltage limited.This completely solves the reduced voltage problem that prior art analogcircuits battle in the newer IC processes.

Noise Advantages:

In the end, it comes down to signal-to-noise ratio. Low power supplyvoltage requirements in ultra-deep-sub-μm IC processes limit the maximumsignal swing to a much smaller number than most analog designers areused to. So with a smaller signal, the noise must be equally small inorder to maintain the desired signal to noise ratio. It is imperativethat noise issues be reduced. This iFET amplifier technology not onlyreduces noise by an amount as would be necessary, but performs farbeyond expectations, delivering ultra-quiet front ends.

1/f noise in the source channel is reduced because the self-bias schemeprovides a high field strength on the source channel's gate, forcingcarriers in the channel to operate below the surface where there is asmoother path (_(fewer obstructions)) than along the surface wherecrystal lattice defects interfere.

1/f noise in the drain channel is also low. Unlike conventional analogdesigns, the gate is self-biased at the half-way point between the powersupply rails as is the drain, while the iPort is within ˜100 millivoltsof the power rail. With the high electric field along the drain channel,and the gate voltage equal to the drain terminal voltage, the carriersare constrained to flow mostly below the channel surface. This keeps thedrain channel out of pinched off conditions, where unwanted 1/f noisewould be generated.

Resistance noise is minimized because the self-bias configuration putsthe complementary pair at its lowest channel resistance operating point.Resistance noise is caused by collisions, between carriers and thesurrounding atoms in the conductor. The lower the resistance is, thefewer the collisions.

Wide band noise (white-noise) would always be an issue in high gain forhigh frequency circuits. While conventional designs adjust the gatevoltage to establish suitable operating point(s), the designs of thepresent invention establish the gate voltage at the optimum point (the“sweet-spot”) and then adjust the load to establish the desiredoperating point. This approach establishes a higher quiescent currentwhere (for reasons explained above) higher current density circuits havelower wide band noise.

High common mode power supply rejection is inherent in the complementaryiFET device structure of the present invention. Signals are with respectto the mid-point instead of being with respect to one of the powersupply rails, similar to an op-amp with its “virtual” ground. Powersupply noise is from one rail to the other, equal and opposite in phasewith respect to each other; thus canceling around the mid-point.

Ground-Loop noise is diminished because the circuit ground is “virtual”(just like in many op-amp circuits), rather than ground being one or theother power supply connections where ground or power noise is conductedinto the analog signal path. . . . In the closed-loop case, “FlyingCapacitors” are often employed. With “flying capacitors” there is nodirect electrical connection between stages, so there is no commonground; virtual or otherwise. The use of “differential decoupling”(flying capacitors) offers transformer like isolation between stages,with the compactness of integrated circuit elements.

Coupled noise from “parasitic induced crosstalk” increases by the squareof the signal amplitude. Unintended capacitive coupling into a 1 voltsignal causes a lot more trouble than with a 100 mV signal, by a factorof 100:1 (square law effect). The small low impedance charge or voltagesignals employed in the analog sections, reduce this capacitive coupledinterference substantially. Nearby Digital signals will, by definition,be high amplitude (rail-to-rail). Good layout practices are still thebest defense against this digital source of noise.

Additional Advantages:

There are a number of additional advantages. For example, bi-directionalcontrol on the iPort means that current can flow in-to as well as out ofthis connection; both directions having a significant and symmetricalcontrol effect on overall channel current. Also, a zero current imposedin the iPort is a valid zero input signal, thus the iPort signals aretruly bidirectional about zero. The iPort has about five (5) orders ofmagnitude more dynamic control range than the gate.

When the low impedance iPort is used to measure an analog Signal, theinput impedance may diminish the input voltage, but the energy transferinto the iPort amplifier is high, especially for low impedance sourcessuch as matching an antenna, transmission line, or many biologicalsignal sources.

When a high-impedance analog amplifier is necessary, the gate is suedfor the input and the amplifier can contain multiple stages for highvoltage gain, while the CiFET can stabilize such an amplifier.

In the CiFET device there are two iPort input signals that preciselysum, thus this structure is an analog adder and can combine the twoinputs at RF frequencies to form a RF mixer using a single CiFET device.

The iFET of the present invention yields an analog structure that issignificantly faster than logic using the same MOS devices. This speedimprovement is due to the fact that the complementary structureexpresses its maximum gain (and highest quiescent current) at itsnatural self-bias point, midway between the power supplies.

Since the iPort voltage does not significantly change, it is immune tothe R/C time constant effects of the surrounding parasitics, thus theiPort (current) input responds faster than the gate (voltage) input.

When used as a data bus sense amplifier on a RAM, the iPort's lowimpedance rapidly senses minute charge transfer without moving the databus voltage significantly. Since the iPort input impedance is low, andthe iPort is terminated with a fixed low voltage, this sense amplifierapproach eliminates the need for pre-charging in the memory readoutcycle. Since the iFET operates at better than logic speed, IFET forsensing charge would decrease the readout time impressively.

Since, in most applications of the CiFET compound device structure ofthe present invention, the output voltage (drain connection point) doesnot vary greatly, and thus making the output immune to the R/C timeconstant effects of the surrounding parasitics. A logic signal is slowerthan analog here because logic signals have to swing from rail to rail.

Drain-induced barrier lowering or (DIBL) threshold reduction is avoidedin the CiFET compound device operating in the analog mode. When gain andthreshold voltage is important, the drains are operating around half ofthe power supply voltage, thus eliminating the higher drain voltageswhere DIBL effects are prevalent.

Definitions of Terms:

iFET: A 4 terminal (plus body) device similar to a Field EffectTransistor but with an additional control connection that causes thedevice to respond to current input stimulus.

source channel: A semiconductor region between iPort diffusion and theSource diffusion. Conduction in this region is enabled by an appropriatevoltage on the Gate.

drain channel: A semiconductor region between Drain diffusion and theiPort diffusion. Conduction in this region is enabled by an appropriatevoltage on the Gate.

CiInv: A single stage, complementary iFET compound device shown in FIG.3a .

super-saturation: an exponential conduction condition similar toweak-inversion, but with high Gate overdrive and forced low voltagealong the conduction channel. FIG. 2d #20.

feed-forward: A technique to present a signal on an output, early on, inanticipation of the ultimate value.

self-biased: Unlike fixed-bias circuits, self-biased circuits adjust tolocal conditions to establish an optimum operating point.

dual: (of a theorem, expression, etc.) related to another by theinterchange of pairs of variables, such as current and voltage as in“trans-conductance” to “trans-resistance.”

trans-resistance: infrequently referred to as mutual resistance, is thedual of trans-conductance. The term is a contraction of transferresistance. It refers to the ratio between a change of the voltage attwo output points and a related change of current through two inputpoints, and is notated as r_(m):

$r_{m} = \frac{\Delta\; V_{out}}{\Delta\; I_{in}}$

The SI unit for trans-resistance is simply the ohm, as in resistance.

For small signal alternating current, the definition is simpler:

trans-conductance is a property of certain electronic components.Conductance is the reciprocal of resistance; trans-conductance is theratio of the current variation at the output to the voltage variation atthe input. it is written as g_(m). For direct current. trans-conductanceis defined as follows:

$g_{m} = \frac{\Delta\; I_{out}}{\Delta\; V_{in}}$

For small signal alternating current, the definition is simpler:

$g_{m} = \frac{i_{out}}{v_{in}}$

Trans-conductance is a contraction of transfer conductance. The old unitof conductance, the mho (ohm spelled backwards), was replaced by the SIunit, the siemens, with the symbol S (1 siemens=1 ampere per volt).

translinear circuit: translinear circuit is a circuit that carries outits function using the translinear principle. These are current-modecircuits that can be made using transistors that obey an exponentialcurrent-voltage characteristic—this includes BJTs and CMOS transistorsin weak-inversion.

Sub-threshold conduction or sub-threshold leakage or sub-threshold draincurrent is the current between the source and drain of a MOSFET when thetransistor is in sub-threshold region, or weak-inversion region, thatis, for gate-to-source voltages below the threshold voltage. Theterminology for various degrees of inversion is described in Tsividis.(Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor(Second Edition ed.). New York: McGraw-Hill. p. 99. ISBN 0-07-065523-5.)

Sub-threshold slope: In the sub-threshold region the drain currentbehavior—though being controlled by the gate terminal—is similar to theexponentially increasing current of a forward biased diode. Therefore aplot of logarithmic drain current versus gate voltage with drain,source, and bulk voltages fixed will exhibit approximately log linearbehavior in this MOSFET operating regime. its slope is the sub-thresholdslope.

Diffusion current: Diffusion current is a current in a semiconductorcaused by the diffusion of charge carriers (holes and/or electrons).Diffusion current can be in the same or opposite direction of a driftcurrent that is formed due to the electric field in the semiconductor.At equilibrium in a p-n junction, the forward diffusion current in thedepletion region is balanced with a reverse drift current, so that thenet current is zero. The diffusion current and drift current togetherare described by the drift-diffusion equation.

Drain-induced barrier lowering: Drain-induced barrier lowering or DIBLis a short-channel effect in MOSFETs referring originally to a reductionof threshold voltage of the transistor at higher drain voltages.

As channel length decreases, the barrier φ_(B) to be surmounted by anelectron from the source on its way to the drain reduces.

As channel length is reduced, the effects of DIBL in the sub-thresholdregion (weak-inversion) show up initially as a simple translation of thesub-threshold current vs. gate bias curve with change in drain-voltage,which can be modeled as a simple change in threshold voltage with drainbias. However, at shorter lengths the slope of the current vs. gate biascurve is reduced, that is, it requires a larger change in gate bias toeffect the same change in drain current. At extremely short lengths, thegate entirely fails to turn the device off These effects cannot bemodeled as a threshold adjustment.

DIBL also affects the current vs. drain bias curve in the active mode,causing the current to increase with drain bias, lowering the MOSFEToutput resistance. This increase is additional to the normal channellength modulation effect on output resistance, and cannot always bemodeled as a threshold adjustment (Drain-induced barrierlowering—https://en.wikipedia.org/wiki/Drain-induced_barrier_lowering).

Analogue electronics

http://en.wikipedia.org/wiki/Analogue_electronics.

What is claimed is:
 1. A solid-state device comprising: a. first andsecond complementary field effect transistors, each comprising a sourceand a drain, wherein the source and drain of the first transistor definea first channel and the source and drain of the second transistor definea second channel; b. a first diffusion (first iPort) that divides thefirst channel into a first source channel segment between the source andthe first iPort and a first drain channel segment between the firstiPort and the drain, and a second diffusion (second iPort) that dividesthe second channel into a second source channel segment between thesource and the second iPort and a second drain channel segment betweenthe second iPort and the drain; c. a common gate port coupled to thefirst source channel segment, the first drain channel segment, thesecond source channel segment and the second drain channel segment; andd. a common drain port electrically connected to the drains of the firstand second transistors.
 2. A solid-state device as in claim 1 whereinthe device further comprises a voltage source connected to the commongate port and is operative to provide a voltage output at the commondrain port.
 3. A solid-state device as in claim 1 wherein the devicefurther comprises a current source connected to at least one of thefirst and second iPorts and is operative to provide a current output atthe common drain port.
 4. A solid-state device as in claim 1 wherein thedevice further comprises a voltage source connected to the common gateport and is operative to provide a current output at the common drainport.
 5. A solid-state device as in claim 1 wherein the device furthercomprises a current source connected to at least one of the first andsecond iPorts and is operative to provide a voltage output at the commondrain port.
 6. A solid-state device as in claim 1 wherein the devicefurther comprises a current source connected to at least one of thefirst and second iPorts and a voltage source connected to the commongate port, and is operative to provide a voltage output at the commondrain port.
 7. A solid-state device as in claim 1 wherein the devicefurther comprises a current source connected to at least one of thefirst and second iPorts and a voltage source connected to the commongate port, and is operative to provide a current output at the commondrain port.
 8. A solid-state device as in claim 7 wherein the device isoperative to also provide a simultaneous voltage output at the commondrain port.
 9. A solid-state device as in claim 1 wherein a ratio of awidth and a length of each of the first source channel segment, thefirst drain channel segment, the second source channel segment and thesecond drain channel segment is adjusted for one or more of impedancematching, gain, noise, and power consumption.